Semiconductor device and electronic appliance

Patent metadata

Field	Value
Publication number	US-9818784-B2
Application number	US-201615146599-A
Country	US
Kind code	B2
Filing date	May 4, 2016
Priority date	Sep 28, 2012
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

The present technique relates to a semiconductor device and an electronic appliance in which the reliability of the fine transistor can be maintained while the signal output characteristic is improved in a device formed by stacking semiconductor substrates.
The semiconductor device includes a first semiconductor substrate, a second semiconductor substrate providing a function different from a function provided by the first semiconductor substrate, and a diffusion prevention film that prevents diffusion of a dangling bond terminating atom used for reducing the interface state of the first semiconductor substrate and the second semiconductor substrate, wherein at least two semiconductor substrates are stacked and the semiconductor substrates are electrically connected to each other, and the first semiconductor substrate and the second semiconductor substrate are stacked with the diffusion prevention film inserted between an interface of the first semiconductor substrate and an interface of the second semiconductor substrate.

First claim

What is claimed is:

1. An imaging device, comprising:
a first semiconductor substrate including a pixel array and a first multilayer wiring layer having a first connecting interconnect embedded in a first insulating layer; and
a second semiconductor substrate including a logic circuit and a second multilayer wiring layer having a second connecting interconnect embedded in a second insulating layer;
wherein the pixel array includes photo detectors and transistors that are formed adjacent to the photo detectors,
wherein the first semiconductor substrate and the second semiconductor substrate are configured such that the first multilayer wiring layer and the second multilayer wiring layer are opposed to one another,
wherein the first semiconductor substrate and the second semiconductor substrate are stacked with a diffusion prevention film inserted between the first semiconductor substrate and the second semiconductor substrate,
wherein an atom supply film is above the transistors, and
wherein the interface state of the first semiconductor substrate is lower than the interface state of the second semiconductor substrate.

2. The imaging device according to claim 1 ,
wherein the diffusion prevention film prevents diffusion of a dangling bond terminating atom used for reducing the interface state of the first semiconductor substrate and the second semiconductor substrate,
wherein the first semiconductor substrate and the second semiconductor substrate are stacked with an atom occlusion film that occludes the dangling bond terminating atom inserted between the diffusion prevention film and the second semiconductor substrate.

3. The imaging device according to claim 2 , wherein
the dangling bond terminating atom is hydrogen, and
a barrier metal covering the second multilayer wiring layer or an extraction electrode in the second semiconductor substrate, which is formed of titanium, is used as the atom occlusion film.

4. The imaging device according to claim 1 , wherein the diffusion prevention film prevents diffusion of a dangling bond terminating atom used for reducing the interface state of the first semiconductor substrate and the second semiconductor substrate, and wherein the diffusion prevention film is a SiN film formed by plasma CVD.

5. The imaging device according to claim 1 , further comprising a third semiconductor substrate provided with a memory circuit, wherein
the second semiconductor substrate is provided between the first semiconductor substrate and the third semiconductor substrate,
the second semiconductor substrate and the third semiconductor substrate are stacked with an additional diffusion prevention film,
the diffusion prevention film and the additional diffusion prevention film prevent diffusion of a dangling bond terminating atom used for reducing the interface state of the first semiconductor substrate and the second semiconductor substrate and prevent diffusion of the dangling bond terminating atom further inserted between an interface of the second semiconductor substrate and an interface of the third semiconductor substrate.

6. The imaging device according to claim 1 , wherein the diffusion prevention film is a SiN film formed by plasma CVD.

7. The imaging device according to claim 1 , wherein the diffusion prevention film is a SiN film formed by LP-CVD.

8. The imaging device according to claim 1 , wherein the diffusion prevention film has a film density of 2.7 g/cm to 3.5 g/cm.

9. The imaging device according to claim 1 , wherein the diffusion prevention film has a thickness of 150 nm or less.

10. The imaging device according to claim 1 , wherein the diffusion prevention film is a SiN film formed by ALD-CVD.

11. The imaging device according to claim 1 ,
wherein the atom supply film supplies a dangling bond terminating atom and the atom supply film is between the first semiconductor substrate and the diffusion prevention film.

12. The imaging device according to claim 11 ,
wherein the dangling bond terminating atom is hydrogen, and an insulating thin film in the first semiconductor substrate formed by a silicon nitride thin film is used as the atom supply film.

13. The imaging device according to claim 1 ,
wherein the diffusion prevention film is a silicon nitride film.

14. The imaging device according to claim 1 ,
wherein the atom supply film is a silicon nitride film.

15. The imaging device according to claim 1 , further comprising:
an insulating film between the atom supply film and the transistors.

16. An imaging device, comprising:
a first semiconductor substrate including a pixel array and a first multilayer wiring layer having a first connecting interconnect embedded in a first insulating layer; and
a second semiconductor substrate including a logic circuit and a second multilayer wiring layer having a second connecting interconnect embedded in a second insulating layer;
wherein the pixel array includes photo detectors and transistors that are formed adjacent to the photo detectors,
wherein the first semiconductor substrate and the second semiconductor substrate are stacked with their multilayer wiring layers not facing each other,
wherein the first semiconductor substrate and the second semiconductor substrate are stacked with a diffusion prevention film inserted between the first semiconductor substrate and the second semiconductor substrate,
wherein an atom supply film is above the transistors, and
wherein the interface state of the first semiconductor substrate is lower than the interface state of the second semiconductor substrate.

17. An electronic appliance, comprising:
a first semiconductor substrate including a pixel array and a first multilayer wiring layer having a first connecting interconnect embedded in a first insulating layer; and
a second semiconductor substrate including a logic circuit and a second multilayer wiring layer having a second connecting interconnect embedded in a second insulating layer;
wherein the first semiconductor substrate and the second semiconductor substrate are configured such that the first multilayer wiring layer and the second multilayer wiring layer are opposed to one another,
wherein the pixel array includes photo detectors and transistors that are formed adjacent to the photo detectors,
wherein the first semiconductor substrate and the second semiconductor substrate are stacked with a diffusion prevention film inserted between the first semiconductor substrate and the second semiconductor substrate,
wherein an atom supply film is above the transistors, and
wherein the interface state of the first semiconductor substrate is lower than the interface state of the second semiconductor substrate.

Assignees

• Sony Corp

Inventors

• Baba Koichi
• Kubodera Takashi
• Miyazaki Toshihiko
• Ammo Hiroaki

Classifications

• H10W72/012

  of bump connectors, dummy bumps or thermal bumps · CPC title

• H10W90/00

  Package configurations · CPC title

• H01L27/1462

  Electricity · mapped topic

• H01L27/14636

  Electricity · mapped topic

• H01L25/167

  Electricity · mapped topic