Semiconductor device and fabricating method thereof

Patent metadata

Field	Value
Publication number	US-9818748-B2
Application number	US-201715440541-A
Country	US
Kind code	B2
Filing date	Feb 23, 2017
Priority date	Jul 16, 2015
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

A semiconductor device is provided. A substrate includes a first region and a second region. A first wire pattern, extending in a first direction, is formed at a first height from the substrate of the first region. A second wire pattern, extending in a second direction, is formed at a second height from the substrate of the second region. The first height is different from the second height. A first gate electrode, surrounding the first wire pattern, extends in a third direction crossing the first direction. A second gate electrode, surrounding the second wire pattern, extends in a fourth direction crossing the second direction. A first gate insulation layer is formed along a circumference of the first wire pattern and a sidewall of the first gate electrode. A second gate insulation layer is formed along a circumference of the second wire pattern and a sidewall of the second gate electrode.

First claim

What is claimed is:

1. A fabricating method of a semiconductor device, the fabricating method comprising:
forming a first fin type structure on a first region of a substrate, wherein the first fin type structure includes a plurality of first semiconductor patterns and a plurality of second semiconductor patterns alternately stacked on each other and extending in a first direction;
forming a second fin type structure on a second region of the substrate, wherein the second fin type structure includes a plurality of third semiconductor patterns and a plurality of fourth semiconductor patterns alternately stacked on each other and extending in a second direction, wherein the plurality of the third semiconductor patterns includes the same material with the plurality of the first semiconductor patterns, and the plurality of the fourth semiconductor patterns includes the same material with the plurality of the second semiconductor patterns;
forming a first dummy gate electrode and a second dummy gate electrode on the first fin type structure and the second fin type structure, respectively, wherein the first dummy gate electrode extends in a third direction crossing the first direction, and the second dummy gate electrode extends in a fourth direction crossing the second direction;
forming a first gate spacer and a second gate spacer on a sidewall of the first dummy gate electrode and a sidewall of the second dummy gate electrode, respectively;
forming a first mask pattern on the second region, wherein the first mask pattern covers the second dummy gate electrode and the second gate spacer, exposing the first dummy gate electrode and the first gate spacer;
removing the first dummy gate electrode and the plurality of the first semiconductor patterns using the first mask pattern to form a first wire pattern group which is made of the plurality of the second semiconductor patterns;
forming a second mask pattern on the first region, wherein the second mask pattern covers the first wire pattern group and the first gate spacer; and
removing the second dummy gate electrode and the plurality of the fourth semiconductor patterns using the second mask pattern to form a second wire pattern group which is made of the plurality of the third semiconductor patterns.

2. The fabricating method of claim 1 , wherein the forming of the first fin type structure and the second fin type structure comprises:
forming a stacked structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked on each other on the substrate;
forming a third mask pattern and a fourth mask pattern on the stacked structure in the first region and the second region; and
etching the stacked structure using the third mask pattern and the fourth mask pattern to form the first fin type structure and the second fin type structure.

3. The fabricating method of claim 2 , wherein a topmost layer of the stacked structure is the first semiconductor layer.

4. The fabricating method of claim 2 , further comprising:
partially removing the plurality of the first semiconductor layers and the plurality of the second semiconductor layers using the first gate spacer as an etching mask; and
forming a first epitaxial layer on the plurality of the first semiconductor layers and the plurality of the second semiconductor layers which are partially removed.

5. The fabricating method of claim 1 , wherein the forming of the first mask pattern comprises:
forming an interlayer insulation layer on the substrate to cover the first dummy gate electrode, the first gate spacer, the second dummy gate electrode and the second gate spacer;
exposing the first dummy gate electrode and the second dummy gate electrode by planarizing the interlayer insulation layer;
forming a mask layer on the planarized interlayer insulation layer to cover the substrate of the first region and the substrate of the second region; and
partially removing the mask layer formed on the substrate of the first region to form the first mask pattern.

6. The fabricating method of claim 1 , wherein the first wire pattern group includes one or more first wire patterns,
the fabricating method further comprising:
forming a first gate insulation layer along circumferences of the first wire patterns and a sidewall of the first gate spacer; and
forming a first gate electrode surrounding the first wire patterns on the first gate insulation layer.

7. A fabricating method of a semiconductor device, the fabricating method comprising:
forming a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked on each other on a substrate;
patterning the plurality of the first semiconductor layers and the plurality of the second semiconductor layers formed on the substrate of a first region to form a plurality of first semiconductor patterns and a plurality of second semiconductor patterns, wherein the plurality of the first semiconductor patterns is made of the plurality of the first semiconductor layers, and wherein the plurality of the second semiconductor patterns is made of the plurality of the second semiconductor layers;
patterning the plurality of the first semiconductor layers and the plurality of the second semiconductor layers formed on the substrate of a second region to form a plurality of third semiconductor patterns and a plurality of fourth semiconductor patterns, wherein the plurality of the third semiconductor patterns is made of the plurality of the first semiconductor layers, and wherein the plurality of the fourth semiconductor patterns is made of the plurality of the second semiconductor layers;
forming a pair of first source/drains on the substrate of the first region, wherein the plurality of the first semiconductor patterns and the plurality of the second semiconductor patterns are interposed between the pair of the first source/drains;
forming a pair of second source/drains on the substrate of the second region, wherein the plurality of the third semiconductor patterns and the plurality of the fourth semiconductor patterns are interposed between the pair of the second source/drains;
removing the plurality of the first semiconductor patterns to form a plurality of first wire patterns, wherein the plurality of the first wire patterns is made of the plurality of the second semiconductor patterns;
removing the plurality of the fourth semiconductor patterns to form a plurality of second wire patterns, wherein the plurality of the second wire patterns is made of the plurality of the third semiconductor patterns;
forming a first gate electrode circumferentially surrounding the plurality of the first wire patterns; and
forming a second gate electrode circumferentially surrounding the plurality of the second wire patterns,
wherein each of the plurality of the first wire patterns is different in height from each of the plurality of the second wire patterns.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Suk Sung-Dae
• Seo Kang-Ill

Classifications

• H01L29/0673

  Electricity · mapped topic

• H01L21/845

  Electricity · mapped topic

• H01L21/823864

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic