Semiconductor arrangement, method for producing a number of chip assemblies, method for producing a semiconductor arrangement and method for operating a semiconductor arrangement

Patent metadata

Field	Value
Publication number	US-9818730-B2
Application number	US-201414477386-A
Country	US
Kind code	B2
Filing date	Sep 4, 2014
Priority date	Sep 5, 2013
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

A semiconductor arrangement includes top and bottom contact plates, a plurality of chip assemblies, a dielectric embedding compound, and a control electrode interconnection structure. Each chip assembly has a semiconductor chip having a semiconductor body. The semiconductor body has a top side and an opposing underside. The top side is spaced apart from the underside in a vertical direction. Each semiconductor chip has a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, a control electrode arranged at the top side, and an electrically conductive top compensation die, arranged on the side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode by means of a top connecting layer. An electric current between the top main electrode and the bottom main electrode can be controlled by means of the control electrode.

First claim

What is claimed is:

1. A semiconductor arrangement, comprising:
a top contact plate and a bottom contact plate;
a plurality of chip assemblies, each of which has:
a semiconductor chip having a semiconductor body, wherein the semiconductor body has a top side and an underside opposite the top side, and wherein the top side is spaced apart from the underside in a vertical direction;
a top main electrode arranged on the top side;
a bottom main electrode arranged on the underside;
a control electrode, which is arranged at the top side and by means of which an electric current between the top main electrode and the bottom main electrode can be controlled; and
an electrically conductive top compensation die, which is arranged on the side of the top main electrode facing away from the semiconductor body and is cohesively and electrically conductively connected to the top main electrode by means of a top connecting layer separate from the top compensation die;

a dielectric embedding compound, by which the chip assemblies are material bonded to one another to form a solid composite, wherein in the case of each of the chip assemblies that side of the top compensation die of the relevant chip assembly which faces away from the semiconductor body is not or at least not completely covered by the embedding compound;
a control electrode interconnection structure, which is arranged on the solid composite and which electrically conductively connects the control electrodes of the chip assemblies to one another;
wherein:
each of the chip assemblies is arranged between the top contact plate and the bottom contact plate such that in the case of each chip assembly the side of the top compensation die facing away from the semiconductor body makes electrical contact with the top contact plate.

2. The semiconductor arrangement of claim 1 , wherein:
(a) each of the chip assemblies has an electrically conductive bottom compensation die, which is arranged on the side of the bottom main electrode facing away from the semiconductor body and is cohesively and electrically conductively connected to the bottom main electrode by means of a bottom connecting layer separate from the bottom compensation die; or
(b) the chip assemblies have a common electrically conductive bottom compensation die, which in the case of each of the chip assemblies is arranged on the side of the bottom main electrode facing away from the semiconductor body and is cohesively and electrically conductively connected to the bottom main electrode by means of a bottom connecting layer separate from the bottom compensation die.

3. The semiconductor arrangement of claim 2 , wherein the bottom connecting layer is embodied as a solder layer, or as an adhesive layer, or as a sintered layer.

4. The semiconductor arrangement of claim 2 , wherein:
in case (a) the bottom compensation dies each have a coefficient of linear thermal expansion of less than 11 ppm/K; or
in case (b) the bottom compensation die has a coefficient of linear thermal expansion of less than 11 ppm/K.

5. The semiconductor arrangement of claim 2 , wherein:
in case (a) the bottom compensation dies each have a thickness of at least 0.4 mm in the vertical direction; or
in case (b) the bottom compensation die has a thickness of at least 0.4 mm.

6. The semiconductor arrangement of claim 1 , wherein:
the top compensation dies each have a coefficient of linear thermal expansion of less than 11 ppm/K.

7. The semiconductor arrangement of claim 1 , wherein the top connecting layer is embodied as a solder layer, or as an adhesive layer, or as a sintered layer.

8. The semiconductor arrangement of claim 1 , further comprising a dielectric spacer ring, which is arranged between the top contact plate and the bottom contact plate and which surrounds the chip assemblies.

9. The semiconductor arrangement of claim 1 , wherein the top contact plate has a contact pedestal on its side facing the bottom contact plate for each of the chip assemblies, the contact pedestal making electrical contact with the side of the top compensation die facing away from the semiconductor body.

10. The semiconductor arrangement of claim 9 , wherein the top contact plate has a contact pedestal on its side facing the bottom contact plate for each of the chip assemblies, the contact pedestal making mechanical contact with the side of the top compensation die facing away from the semiconductor body.

11. The semiconductor arrangement of claim 1 , wherein each of the chip assemblies has an electrically conductive contact piece, which is arranged between the control electrode of the relevant chip assembly and the control electrode interconnection structure and electrically conductively connects them to one another.

12. The semiconductor arrangement of claim 1 , wherein the control electrode interconnection structure is arranged between the top contact plate and the solid composite.

13. The semiconductor arrangement of claim 1 , wherein the control electrode interconnection structure is embodied as a printed circuit board, or as a structured metallization layer.

14. The semiconductor arrangement of claim 1 , wherein the semiconductor bodies of directly adjacent chip assemblies have a spacing of at least 300 μm.

15. The semiconductor arrangement of claim 1 , wherein in the case of each of the chip assemblies the top compensation die has a thickness of at least 0.4 mm in the vertical direction.

16. The semiconductor arrangement of claim 1 , wherein the control electrode interconnection structure contains at least one passive component which:
is arranged on a conductor structure of the control electrode interconnection structure; and/or
constitutes a constituent part of the conductor structure of the control electrode interconnection structure.

17. The semiconductor arrangement of claim 1 , wherein the control electrode interconnection structure has a conformally deposited conductor structure.

18. The semiconductor arrangement of claim 17 , wherein the conformally deposited conductor structure has a thickness in the range of 30 μm to 70 μm.

19. A method for producing a semiconductor assembly, the method comprising:
providing a carrier;
providing a dielectric embedding compound;
providing a plurality of chip assemblies, each of which has:
a semiconductor chip having a semiconductor body, wherein the semiconductor body has a top side and an underside opposite the top side, and wherein the top side is spaced apart from the underside in a vertical direction;
a top main electrode arranged on the top side;
a bottom main electrode arranged on the underside;
a control electrode, which is arranged at the top side and by means of which an electric current between the top main electrode and the bottom main electrode can be controlled; and
an electrically conductive top compensation die, which is arranged on the side of the top main electrode facing away from the semiconductor body and is cohesively and electrically conductively connected to the top main electrode by means of a top connecting layer separate from the top compensation die; and

arranging the chip assemblies alongside one another on the carrier;
embedding the chip assemblies arranged on the carrier into the embedding compound and subsequently curing the embedding compound, such that the chip assemblies are fixedly connected to one another by the embedding compound and together with the embedding compound form a solid composite;
removing a top cover layer of the solid composite from the solid composi

Assignees

• Infineon Technologies Ag

Inventors

• Beer Gottfried
• Escher-Poeppel Irmgard
• Hoegerl Juergen
• Hohlfeld Olaf
• Kanschat Peter

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10W72/01904

  using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title