Chip stack cooling structure

Patent metadata

Field	Value
Publication number	US-9818726-B2
Application number	US-201514981120-A
Country	US
Kind code	B2
Filing date	Dec 28, 2015
Priority date	Dec 28, 2015
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

An apparatus comprises a first die, a thermal cooler formed over at least a portion of the first die, a second die formed over at least a portion of the thermal cooler, and a plurality of through-silicon vias providing electrical connections between the first die and the second die. The thermal cooler comprises a plurality of fluid channels for fluid cooling of the first die and the second die, the plurality of fluid channels being formed horizontally through the thermal cooler. The plurality of through-silicon vias are formed vertically through the first die, the thermal cooler and the second die.

First claim

The invention claimed is:

1. An apparatus comprising:
a first die;
a thermal cooler disposed over at least a portion of the first die;
a second die disposed over at least a portion of the thermal cooler; and
a plurality of through-silicon vias providing electrical connections between the first die and the second die;
wherein the thermal cooler comprises a plurality of fluid channels for fluid cooling of the first die and the second die, each of the plurality of fluid channels disposed horizontally through the thermal cooler;
wherein the plurality of through-silicon vias are disposed vertically through the first die, the thermal cooler and the second die;
wherein the thermal cooler comprises a first silicon wafer die half and a second silicon wafer die half, each of the first silicon wafer die half and the second silicon wafer die half comprising a plurality of vias disposed in outer edge portions thereof and a plurality of trenches disposed in an inner portion thereof, the outer edge portions of the first silicon wafer die half and the second silicon wafer die half surrounding the inner portions of the first silicon wafer die half and the second silicon wafer die half, respectively; and
wherein the first silicon wafer die half and the second silicon wafer die half are thermo-compression copper bonded to connect the plurality of vias disposed in the outer edge portions thereof to one another forming connected pairs of vias and to connect the plurality of trenches disposed in the inner portions thereof to one another forming connected pairs of trenches, each connected pair of trenches providing one of the plurality of microchannel coolers and each connected pair of vias providing a portion of one of the plurality of through-silicon vias.

2. The apparatus of claim 1 , wherein the first die and the thermal cooler are bonded via a thermal interface material providing thermal heat conduction.

3. The apparatus of claim 1 , wherein the plurality of through-silicon vias connect the first die and the thermal cooler via micro controlled-collapse chip-connection interconnects.

4. The apparatus of claim 1 , wherein the plurality of through-silicon vias connect the first die and the thermal cooler via copper-to-copper bonding.

5. The apparatus of claim 1 , further comprising at least one lead routed through at least one of the through-silicon vias, wherein the at least one lead comprises at least one of an electrical lead and a power lead.

6. The apparatus of claim 1 , further comprising:
an additional thermal cooler disposed over at least a portion of the second die; and
a third die disposed over at least a portion of the additional thermal cooler;
wherein the thermal cooler and the additional thermal cooler each overhang edges of the first die, the second die and the third die; and
wherein a first overhang of the thermal cooler is different than a second overhang of the additional thermal cooler.

7. The apparatus of claim 1 , wherein the plurality of fluid channels are connected to one another via at least one common fluid channel comprising at least one fluid inlet and at least one fluid outlet.

8. The apparatus of claim 1 , wherein the plurality of fluid channels comprise a liquid coolant.

9. The apparatus of claim 8 , wherein the liquid coolant comprises a dielectric liquid.

10. The apparatus of claim 8 , wherein the liquid coolant comprises water.

11. The apparatus of claim 1 , further comprising a substrate, the substrate providing fluid connections to portions of the thermal cooler which overhang edges of the first die and the second die.

12. The apparatus of claim 1 , wherein walls of the trenches in each of the first silicon wafer die half and the second silicon wafer die half are textured increasing a surface area thereof.

13. The apparatus of claim 1 , further comprising an oxide disposed on walls of the vias in each of the first silicon wafer die half and the second silicon wafer die half.

14. The apparatus of claim 1 , wherein each of the plurality of through-silicon vias is disposed in the outer edge portions of the thermal cooler and each of the plurality of fluid channels is disposed in the inner portion of the thermal cooler.

15. The apparatus of claim 14 , wherein the outer edge portions of the thermal cooler do not overlap the inner portion of the thermal cooler.

16. An integrated circuit comprising:
a chip stack comprising:
at least a first die and a second die; and
a thermal cooler interposed between the first die and the second die;

wherein the chip stack comprises a plurality of through-silicon vias providing electrical connections between the first die and the second die;
wherein the thermal cooler comprises a plurality of fluid channels for fluid cooling of the first die and the second die, each of the plurality of fluid channels being disposed horizontally through the thermal cooler;
wherein the plurality of through-silicon vias are disposed vertically through the first die, the thermal cooler and the second die;
wherein the thermal cooler comprises a first silicon wafer die half and a second silicon wafer die half, each of the first silicon wafer die half and the second silicon wafer die half comprising a plurality of vias disposed in outer edge portions thereof and a plurality of trenches disposed in an inner portion thereof, the outer edge portions of the first silicon wafer die half and the second silicon wafer die half surrounding the inner portions of the first silicon wafer die half and the second silicon wafer die half, respectively; and
wherein the first silicon wafer die half and the second silicon wafer die half are thermo-compression copper bonded to connect the plurality of vias disposed in the outer edge portions thereof to one another forming connected pairs of vias and to connect the plurality of trenches disposed in the inner portions thereof to one another forming connected pairs of trenches, each connected pair of trenches providing one of the plurality of microchannel coolers and each connected pair of vias providing a portion of one of the plurality of through-silicon vias.

17. A method comprising:
forming a first die;
forming a thermal cooler over at least a portion of the first die;
forming a second die over at least a portion of the thermal cooler;
forming a plurality of through-silicon vias vertically through the first die, the thermal cooler and the second die, the plurality of through-silicon vias providing electrical connections between the first die and the second die; and
forming a plurality of fluid channels horizontally through the thermal cooler, the plurality of fluid channels providing fluid cooling of the first die and the second die;
wherein the thermal cooler comprises a first silicon wafer die half and a second silicon wafer die half, each of the first silicon wafer die half and the second silicon wafer die half comprising a plurality of vias disposed in outer edge portions thereof and a plurality of trenches disposed in an inner portion thereof, the outer edge portions of the first silicon wafer die half and the second silicon wafer die half surrounding the inner portions of the first silicon wafer die half and the second silicon wafer die half, respectively; and

wherein the first silicon wafer die half and the second silicon wafer die half are thermo-compression copper bonded to connect the plurality of vias disposed in the outer edge portions thereof to one another forming connected pairs of vias and to connect the plurality of trenches disposed in the inner portions thereof to one another formin

Assignees

• IBM

Inventors

• Chainer Timothy J

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title