Semiconductor integrated circuit device

Patent metadata

Field	Value
Publication number	US-9818715-B2
Application number	US-201414523862-A
Country	US
Kind code	B2
Filing date	Oct 25, 2014
Priority date	Oct 28, 2013
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

A semiconductor integrated circuit chip, in which multi-core processors are integrated, is usually mounted over an organic wiring board by FC bonding to form a BGA package by being integrated with the substrate. In such a structure, power consumption is increased, and hence the power supplied only from a peripheral portion of the chip is insufficient, so that a power supply pad is also provided in the chip central portion. However, because of an increase in the wiring associated with the integration of a plurality of CPU cores, etc., there occurs a portion between the peripheral portion and the central portion of the chip, where a power supply pad cannot be arranged. According to the outline of the present application, in a semiconductor integrated circuit device such as a BGA, etc., in which a semiconductor chip is mounted over an interposer, such as a multilayer organic wiring board, in a face-up manner, a first group of metal through electrodes, which are provided in the semiconductor chip to supply a power supply potential to a core circuit, etc., and a first metal land over the interposer are interconnected by a first conductive adhesive member film.

First claim

What is claimed is:

1. A semiconductor integrated circuit device comprising:
(a) a first organic wiring board having a top surface and a rear surface;
(b) a first metal land formed over the top surface of the first organic wiring board;
(c) a semiconductor chip that has a first main surface and a second main surface and is mounted on the top surface side of the first organic wiring board via the second main surface;
(d) a first integrated circuit region and a second integrated circuit region, which are provided on the first main surface side of the semiconductor chip;
(e) a first group of metal through electrodes that penetrate a space between the first main surface and the second main surface of the semiconductor chip to supply a power supply potential to the first integrated circuit region; and
(f) a first conductive adhesive member film that is provided between the top surface of the first organic wiring board and the second main surface of the semiconductor chip to electrically connect the first metal land and the first group of the metal through electrodes with one another.

2. The semiconductor integrated circuit device according to claim 1 ,
wherein the first integrated circuit region is an internal circuit region and the second integrated circuit region is an I/O circuit region.

3. The semiconductor integrated circuit device according to claim 2 further comprising:
(g) a first bonding pad formed over the first main surface side of the semiconductor chip to supply a power supply potential to the second integrated circuit region;
(h) a second metal land formed over the top surface of the first organic wiring board; and
(i) a first bonding wire connecting the first bonding pad and the second metal land with one another.

4. The semiconductor integrated circuit device according to claim 3 further comprising:
(j) a third metal land formed over the top surface of the first organic wiring board;
(k) a second group of metal through electrodes that penetrate a space between the first main surface and the second main surface of the semiconductor chip;
(l) a second conductive adhesive member film that is provided between the top surface of the first organic wiring board and the second main surface of the semiconductor chip to electrically connect the third metal land and the second group of the metal through electrodes with one another;
(m) a second bonding pad formed over the first main surface side of the semiconductor chip to supply a ground potential to the second integrated circuit region;
(n) a fourth metal land formed over the top surface of the first organic wiring board; and
(o) a second bonding wire connecting the second bonding pad and the fourth metal land with one another,
wherein the second group of the metal through electrodes supply a ground potential to the first integrated circuit region.

5. The semiconductor integrated circuit device according to claim 4 ,
wherein the first conductive adhesive member film and the second conductive adhesive member film include a conductive paste member.

6. The semiconductor integrated circuit device according to claim 5 ,
wherein the first conductive adhesive member film and the second conductive adhesive member film are isolated, in plan view, from each other by a solder resist film over the top surface of the first organic wiring board.

7. The semiconductor integrated circuit device according to claim 6 ,
wherein a lower end of each of the first group of the metal through electrodes and the first conductive adhesive member film are directly and electrically connected with one another, while a lower end of each of the second group of the metal through electrodes and the second conductive adhesive member film are directly and electrically connected with one another.

8. The semiconductor integrated circuit device according to claim 7 further comprising:
(p) a third I/O signal bonding pad formed over the first main surface side of the semiconductor chip to exchange signals with the second integrated circuit region;
(q) a fifth metal land formed over the top surface of the first organic wiring board; and
(r) a third bonding wire connecting the third bonding pad and the fifth metal land with one another.

9. The semiconductor integrated circuit device according to claim 4 ,
wherein the first conductive adhesive member film and the second conductive adhesive member film include a solder member.

10. The semiconductor integrated circuit device according to claim 4 further comprising:
(s) a memory chip laminated body for interconnecting groups of metal through electrodes, which is mounted over the first main surface of the semiconductor chip.

11. The semiconductor integrated circuit device according to claim 1 , wherein each metal through electrode is embedded within the semiconductor chip and extends from the second main surface to at least a region in between the first and second main surfaces.

12. The semiconductor integrated circuit device according to claim 1 ,
wherein each metal through electrode comprises a first portion embedded within the semiconductor chip and a second portion extending from the second main surface toward the top surface of the first organic wiring board,
wherein a barrier metal film covers a sidewall of the second portion of each metal through electrode,
wherein a liner insulating film covers a portion of a sidewall of the barrier metal film, and
wherein a rear surface insulating film covers portions of the second main surface and a sidewall of the liner insulating film.

13. The semiconductor integrated circuit device according to claim 1 , wherein, in plan view, the first integrated circuit region is between facing portions of the second integrated circuit region.

14. A semiconductor integrated circuit device comprising:
(a) a first organic wiring board having a top surface and a rear surface;
(b) a first metal land formed over the top surface of the first organic wiring board;
(c) a semiconductor chip that has a first main surface and a second main surface and is flip-chip bonded to a portion on the top surface side of the first organic wiring board via a first group of bump electrodes and a second group of bump electrodes, which are formed over the first main surface;
(d) a first integrated circuit region and a second integrated circuit region, which are provided on the first main surface side of the semiconductor chip;
(e) a first group of metal through electrodes that penetrate a space between the first main surface and the second main surface of the semiconductor chip; and
(f) a first bonding wire stretched between the second main surface of the semiconductor chip and the top surface of the first organic wiring board to electrically connect the first metal land and the first group of the metal through electrodes with one another.

15. The semiconductor integrated circuit device according to claim 14 ,
wherein the first integrated circuit region is an internal circuit region and the second integrated circuit region is an I/O circuit region.

16. The semiconductor integrated circuit device according to claim 15 ,
wherein the first group of the bump electrodes supply a power supply potential to the first integrated circuit region.

17. The semiconductor integrated circuit device according to claim 16 ,
wherein the first group of the metal through electrodes supply a power supply potential to the second integrated circuit region.

18. The semiconductor integrated circuit device according to claim 17 ,
wherein the second group of

Assignees

• Renesas Electronics Corp

Inventors

• Yamada Jun
• Betsui Takafumi

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title