Method for forming Fin field effect transistor (FinFET) device structure

Patent metadata

Field	Value
Publication number	US-9818648-B2
Application number	US-201615236765-A
Country	US
Kind code	B2
Filing date	Aug 15, 2016
Priority date	Mar 26, 2015
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

Methods for forming the fin field effect transistor (FinFET) device structure are provided. The method includes forming first fin structures and second fin structures on a first region and a second region of a substrate, respectively, and a number of the first fin structures is greater than a number of the second fin structures. The method also includes forming a sacrificial layer on the first fin structures and the second fin structures and performing an etching process to the sacrificial layer to form an isolation structure on the substrate.

First claim

What is claimed is:

1. A method for forming a fin field effect transistor (FinFET) device structure, comprising:
forming first fin structures and second fin structures on a first region and a second region of a substrate, respectively, wherein a number of the first fin structures is greater than a number of the second fin structures;
forming a sacrificial layer on the first fin structures and the second fin structures; and
performing an etching process to the sacrificial layer to form an isolation structure on the substrate;
forming a dummy gate structure on a middle portion of the first fin structures and the second fin structures;
removing a portion of a top portion of the first fin structures to form a cavity;
forming a source/drain structure in the cavity and on the cavity; and
forming the inter-layer dielectric (ILD) structure on the S/D structure and the dummy gate structure.

2. The method for forming the fin field effect transistor (FinFET) device structure as claimed in claim 1 , wherein forming the first fin structures and the second fin structures on the first region and the second region, respectively comprises:
forming a pad layer on the substrate;
forming a hard mask layer on the pad layer;
forming a photoresist layer on the hard mask layer;
patterning the photoresist layer to form a patterned photoresist layer; and
patterning the hard mask layer and the pad layer by using the patterned photoresist layer as a mask to form the patterned hard mask layer and the patterned pad layer;
etching a portion of the substrate by using the patterned hard mask layer and the patterned pad layer as a mask.

3. The method for forming the fin field effect transistor (FinFET) device structure as claimed in claim 1 , before the sacrificial layer on the first fin structures and the second fin structures, further comprising:
forming a hard mask layer over the first fin structures and the second fin structures;
forming a dielectric layer on the first fin structures and the second fin structures; and
thinning the dielectric layer to expose a top surface of the hard mask layer, such that a top surface of the dielectric layer is level with the top surface of the hard mask layer.

4. The method for forming the fin field effect transistor (FinFET) device structure as claimed in claim 1 , wherein forming the first fin structures and the second fin structures on the first region and the second region comprises:
forming third fin structures on the second region, wherein the number of the first fin structures on the first region is equal to a sum of a number of the third fin structures and the number of the second fin structure on the second region; and
removing the third fin structures, such that the number of the first fin structures on the first region is greater than the number of the second fin structures on the second region.

5. The method for forming the fin field effect transistor (FinFET) device structure as claimed in claim 1 , wherein the sacrificial layer has a first thickness which is measured from a top surface of the first fin structures to a top surface of the sacrificial layer, and the first thickness is in a range from about 10 nm to about 50 nm.

6. The method for forming the fin field effect transistor (FinFET) device structure as claimed in claim 1 , further comprising:
removing the dummy gate structure to form a trench;
forming a high-k dielectric layer in the trench; and
forming a metal gate electrode layer on the high-k dielectric layer.

7. The method for forming the fin field effect transistor (FinFET) device structure as claimed in claim 1 , further comprising:
forming additional fin structures between two adjacent second fin structures on the second region, wherein the additional fin structures are covered by the isolation structure.

8. A method for forming a fin field effect transistor (FinFET) device structure, comprising:
forming first fin structures and the second fin structures on a first region and a second region of a substrate, respectively, wherein forming the first fin structures and the second fin structures on the first region and the second region comprises:
forming third fin structures on the second region, wherein the number of the first fin structures on the first region is equal to a sum of a number of the third fin structures and the number of the second fin structure on the second region; and
removing the third fin structures, such that the number of the first fin structures on the first region is greater than the number of the second fin structures on the second region;

forming a hard mask layer over the first fin structures and the second fin structures;
forming a dielectric layer on the hard mask layer; and
performing an etching process to the dielectric layer to form an isolation structure on the substrate, wherein the isolation structure is lower than a top surface of the first fin structures and the second fin structures.

9. The method for forming the fin field effect transistor (FinFET) device structure as claimed in claim 8 , further comprising:
forming a pad layer on the first fin structures and the second fin structures before the step of forming the hard mask layer.

10. The method for forming the fin field effect transistor (FinFET) device structure as claimed in claim 8 , wherein the dielectric layer has a first thickness which is measured from a top surface of the first fin structures to a top surface of the dielectric layer, and the first thickness is in a range from about 10 nm to about 50 nm.

11. The method for forming the fin field effect transistor (FinFET) device structure as claimed in claim 8 , further comprising:
forming a dummy gate structure on a middle portion of the first fin structures and the second fin structures;
removing the top portion of the first fin structures to form a cavity;
forming a source/drain structure in the cavity and on the cavity; and
forming an inter-layer dielectric (ILD) structure on the source/drain structure and the dummy gate structure.

12. The method for forming the fin field effect transistor (FinFET) device structure as claimed in claim 11 , further comprising:
removing the dummy gate structure to form a trench;
forming a high-k dielectric layer in the trench; and
forming a metal gate electrode layer on the high-k dielectric layer.

13. A method for forming a fin field effect transistor (FinFET) device structure, comprising:
forming first fin structures and second fin structures on a first region and a second region of a substrate, respectively;
forming a hard mask layer over the first fin structures and the second fin structures;
forming a dielectric layer on the hard mask layer;
thinning the dielectric layer to expose a top surface of the hard mask layer, such that a top surface of the dielectric layer is level with a top surface of the hard mask layer;
removing the hard mask layer to expose top surfaces of the first fin structures and top surfaces of the second fin structures;
forming a sacrificial layer on the dielectric layer, the first fin structures and the second fin structures; and
performing an etching process to the sacrificial layer to form an isolation structure on the substrate.

14. The method for forming the fin field effect transistor (FinFET) device structure as claimed in claim 13 , wherein forming the first fin structures and the second fin structures on the first region and the second region, respectively comprises:
forming a pad layer on the substrate;
forming a hard mask layer on the pad layer;
forming a photoresist layer on the hard mask layer;
patterning the photor

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chao Yi-Cheng
• Chang Chai-Wei
• Wu Po-Chi
• Li Jung-Jui

Classifications

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H01L21/76224

  Electricity · mapped topic

• H01L21/823431 Primary

  Electricity · mapped topic