Oxide TFT, preparation method thereof, array substrate, and display device

US9818605B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9818605-B2
Application numberUS-201314387390-A
CountryUS
Kind codeB2
Filing dateJul 2, 2013
Priority dateMar 1, 2013
Publication dateNov 14, 2017
Grant dateNov 14, 2017

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Abstract

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An Oxide TFT, a preparation method thereof, an array substrate and a display device are described. The method includes forming a gate electrode, a gate insulating layer, a channel layer, a barrier layer, as well as a source electrode and a drain electrode on a substrate; the channel layer is formed by depositing an amorphous oxide semiconductor film in a first mixed gas containing H 2 , Ar and O 2 . By depositing a channel layer in a first mixed gas containing H 2 , Ar and O 2 , the hysteresis phenomenon of the TFT can be mitigated effectively to improve the display quality of the display panel.

First claim

Opening claim text (preview).

The invention claimed is: 1. A preparation method of an Oxide TFT, comprising forming a gate electrode, a gate insulating layer, a channel layer as well as a source electrode and a drain electrode on a substrate, wherein the channel layer is formed by depositing an amorphous oxide semiconductor film in a first mixed gas containing H 2 , Ar and O 2 , wherein forming of the channel layer comprises: depositing a first amorphous oxide semiconductor film having a thickness of 50-80 nm in a mixed gas of Ar and O 2 ; subsequently depositing a second amorphous oxide semiconductor film having a thickness of 10-20 nm in a mixed gas of Ar and H 2 , wherein during a transition period the mixed gas of Ar and O 2 is mixed with gases of Ar and H 2 , so that a final mixed gas of Ar and H 2 containing only Ar and H 2 is obtained after depositing the second amorphous oxide semiconductor film; and conducting a patterning process on the first amorphous oxide semiconductor film and the second amorphous oxide semiconductor film to form the channel layer, in the mixed gas of Ar and O 2 , Ar and O 2 are contained at a ratio of 15:1-20:1; in the mixed gas of Ar and H 2 , Ar and H 2 are contained at a ratio of 9:1-2:1. 2. The preparation method according to claim 1 , wherein the source electrode and the drain electrode are formed by depositing in a second mixed gas containing H 2 and Ar; the source electrode and the drain electrode are formed by using an amorphous oxide material which presents conductor characteristic. 3. The preparation method according to claim 1 , wherein, in the mixed gas of Ar and O 2 , Ar and O 2 are contained at a ratio of 19:1; in the mixed gas of Ar and H 2 , Ar and H 2 are contained at a ratio of 9:1. 4. The preparation method according to claim 2 , wherein forming of the source electrode and the drain electrode comprises: depositing a first amorphous oxide film having a thickness of 10-20 nm in a mixed gas of Ar and H 2 which are contained at a ratio of 9:1-2:1; subsequently depositing a second amorphous oxide film having a thickness of 180-200 nm in a mixed gas of Ar and H 2 which are contained at a ratio of 3:2-1:1; and conducting a patterning process on the first amorphous oxide film and the second amorphous oxide film to form the source and the drain. 5. The preparation method according to claim 4 wherein, when depositing the first amorphous oxide film, Ar and H 2 are contained at a ratio of 2:1. 6. The preparation method according to claim 1 , wherein the amorphous oxide material is Indium Gallium Zinc Oxide (IGZO). 7. An array substrate, comprising an Oxide TFT according to claim 1 . 8. A display device, comprising the array substrate according to claim 7 . 9. The array substrate according to claim 7 , wherein the amorphous oxide material is Indium Gallium Zinc Oxide (IGZO). 10. The preparation method according to claim 2 , wherein the amorphous oxide material is Indium Gallium Zinc Oxide (IGZO). 11. The preparation method according to claim 1 , wherein the amorphous oxide material is Indium Gallium Zinc Oxide (IGZO). 12. The preparation method according to claim 3 , wherein the amorphous oxide material is Indium Gallium Zinc Oxide (IGZO). 13. The preparation method according to claim 4 , wherein the amorphous oxide material is Indium Gallium Zinc Oxide (IGZO). 14. The preparation method according to claim 5 , wherein the amorphous oxide material is Indium Gallium Zinc Oxide (IGZO). 15. A preparation method of an Oxide TFT, comprising forming a gate electrode, a gate insulating layer, a channel layer as well as a source electrode and a drain electrode on a substrate, wherein the channel layer is formed by depositing an amorphous oxide semiconductor film in a first mixed gas containing H 2 , Ar and O 2 , wherein forming of the channel layer comprises: depositing a first amorphous oxide semiconductor film in a mixed gas of Ar and O 2 ; subsequently depositing a second amorphous oxide semiconductor film in a mixed gas of Ar and H 2 , wherein during a transition period the mixed gas of Ar and O 2 is mixed with gases of Ar and H 2 , so that a final mixed gas of Ar and H 2 containing only Ar and H 2 is obtained after depositing the second amorphous oxide semiconductor film; and conducting a patterning process on the first amorphous oxide semiconductor film and the second amorphous oxide semiconductor film to form the channel layer.

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Inventors

Classifications

  • being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

  • being oxide semiconducting materials (Group IIB-VIA semiconductors H10P14/3224) · CPC title

  • Oxides · CPC title

  • of semiconductor materials · CPC title

  • Oxides · CPC title

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What does patent US9818605B2 cover?
An Oxide TFT, a preparation method thereof, an array substrate and a display device are described. The method includes forming a gate electrode, a gate insulating layer, a channel layer, a barrier layer, as well as a source electrode and a drain electrode on a substrate; the channel layer is formed by depositing an amorphous oxide semiconductor film in a first mixed gas containing H 2 , Ar and …
Who is the assignee on this patent?
Boe Technology Group Co Ltd, Beijing Boe Optoelectronics Tech Co Ltd, Bejing Boe Optoelectronics Tech Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10P14/3426. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 14 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).