Image display device and electronic appliance

US9818340B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9818340-B2
Application numberUS-201113064195-A
CountryUS
Kind codeB2
Filing dateMar 10, 2011
Priority dateAug 18, 2006
Publication dateNov 14, 2017
Grant dateNov 14, 2017

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

An image display device includes: a pixel array part formed of first to fourth scanning lines arranged in rows, signal lines arranged in columns, pixel circuits in a matrix connected to the scanning lines and signal lines, and a plurality of power source lines which supplies first to third potentials necessary for the operations of pixel circuit; a signal part which supplies a video signal to the signal lines; and a scanner part which supplies a control signal to the first to fourth scanning lines, and in turn scans the pixel circuit for every row, wherein the pixel circuits include a sampling transistor, a drive transistor, first to third switching transistors, a pixel capacitance, and a light emitting device, and a channel length of the drive transistor is made longer than a channel length of the switching transistors to suppress fluctuations in threshold voltage.

First claim

Opening claim text (preview).

What is claimed is: 1. An image display device comprising: scanning lines arranged in rows; signal lines arranged in columns; a scanner part configured to supply a control signal to the scanning lines; and pixel circuits in a matrix connected to the scanning lines and the signal lines, wherein at least one of the pixel circuits includes a sampling transistor, a drive transistor, a pixel capacitor, a light emitting device, a first switching transistor directly connected between a first voltage line and the pixel capacitor, a second switching transistor directly connected between a second voltage line and the light emitting device, and a third switching transistor directly connected between a third voltage line and the drive transistor, the sampling transistor is configured to supply a signal potential from the signal line to the pixel capacitor, the pixel capacitor connected between a current terminal and a control terminal of the drive transistor, and a channel length of the drive transistor is made longer than a channel length of each of the three switching transistors and transistors in the scanner part. 2. The image display device according to claim 1 , wherein the channel length of the drive transistor is set to at least 10 μm. 3. The image display device according to claim 1 , wherein in at least one of the pixel circuits, the channel length of the drive transistor is set so that during a light emission period, a source potential and a gate potential of the drive transistor rise together, wherein a voltage difference between the gate potential and the source potential stays constant throughout the light emission period. 4. The image display device according to claim 1 , wherein a current is configured to be applied to the pixel capacitor via the drive transistor while the signal potential is being sampled. 5. The image display device according to claim 1 , wherein the drive transistor is formed by a low temperature poly-silicon process. 6. An electronic appliance having the image display device according to claim 1 . 7. An image display device comprising: scanning lines arranged in rows; signal lines arranged in columns; a scanner part configured to supply a control signal to the scanning lines; and pixel circuits in a matrix connected to the scanning lines and the signal lines, wherein at least one of the pixel circuits includes a sampling transistor, a drive transistor, a pixel capacitor, a light emitting device, a first switching transistor directly connected between a first voltage line and the pixel capacitor, a second switching transistor directly connected between a second voltage line and the light emitting device, and a third switching transistor directly connected between a third voltage line and the drive transistor, the sampling transistor is configured to supply a signal potential from the signal line to the pixel capacitor, the pixel capacitor connected between a current terminal and a control terminal of the drive transistor, and a channel length of the drive transistor is made longer than a channel length of each of the three switching transistors and transistors in the scanner part. 8. The image display device according to claim 7 , wherein the channel length of the drive transistor is set to at least 10 μm. 9. The image display device according to claim 7 , wherein in at least one of the pixel circuits, the channel length of the drive transistor is set so that during a light emission period, a source potential and a gate potential of the drive transistor rise together, wherein a voltage difference between the gate potential and the source potential stays constant throughout the light emission period. 10. The image display device according to claim 7 , wherein a current is configured to be applied to the pixel capacitor via the drive transistor while the signal potential is being sampled. 11. The image display device according to claim 7 , wherein the drive transistor is formed by a low temperature poly-silicon process. 12. An electronic appliance having the image display device according to claim 7 . 13. An image display device comprising: scanning lines arranged in rows; signal lines arranged in columns; a scanner part configured to supply a control signal to the scanning lines; and pixel circuits in a matrix connected to the scanning lines and the signal lines, wherein at least one of the pixel circuits includes a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a drive transistor, a pixel capacitor, and a light emitting device; the first switching transistor is configured to supply a signal potential to the pixel capacitor, a gate of the first switching transistor is connected to a first scanning line; the second switching transistor is directly connected between a first voltage line and the pixel capacitor and is configured to supply a first predetermined potential to the pixel capacitor, a gate of the second switching transistor is connected to a second scanning line; the third switching transistor is directly connected between a second voltage line and the light emitting device and is configured to supply a second predetermined potential to an anode of the light emitting device, a gate of the third switching transistor is connected to a third scanning line; the fourth switching transistor is directly connected between a third voltage line and the drive transistor and is configured to supply a third predetermined potential to the drive transistor, a gate of the fourth switching transistor is connected to a fourth scanning line; and a channel length of the drive transistor is longer than a channel length of each of the first, second, third, fourth switching transistor, and transistors in the scanner part. 14. The image display device according to claim 13 , wherein, while the signal potential is sampled, the drive transistor is configured to apply a negative feedback of an output current of the drive transistor to a first terminal of the pixel capacitor. 15. The image display device according to claim 14 , wherein a potential of the first terminal of the pixel capacitor is increased towards a potential of a second terminal of the pixel capacitor by the negative feedback. 16. The image display device according to claim 13 , wherein the channel length of the drive transistor is at least 10μm. 17. The image display device according to claim 13 , wherein the channel length of the drive transistor is set so that during a light emission period, a source potential of the drive transistor and a gate potential of the drive transistor rise together, wherein a voltage difference between the gate potential and the source potential stays constant throughout the light emission period. 18. The image display device according to claim 13 , wherein a current is configured to be applied to the pixel capacitor via the drive transistor while the signal potential is being sampled. 19. The image display device according to claim 13 , wherein the drive transistor is formed by a low temperature poly-silicon process. 20. The image display device according to claim 13 , wherein the second predetermined potential is lower than a threshold voltage of the light emitting device. 21. An electronic appliance having the image display device according to claim 13 .

Assignees

Inventors

Classifications

  • characterised by the active materials · CPC title

  • characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

  • for control of overall brightness · CPC title

  • with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

  • Electricity · mapped topic

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9818340B2 cover?
An image display device includes: a pixel array part formed of first to fourth scanning lines arranged in rows, signal lines arranged in columns, pixel circuits in a matrix connected to the scanning lines and signal lines, and a plurality of power source lines which supplies first to third potentials necessary for the operations of pixel circuit; a signal part which supplies a video signal to t…
Who is the assignee on this patent?
Yamashita Junichi, Mitomi Yutaka, Minami Tetsuo, and 2 more
What technology area does this patent fall under?
Primary CPC classification G09G3/3233. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Nov 14 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).