Neural network circuit and learning method thereof

Patent metadata

Field	Value
Publication number	US-9818057-B2
Application number	US-201514611145-A
Country	US
Kind code	B2
Filing date	Jan 30, 2015
Priority date	Jul 4, 2013
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

In a neural network circuit element, a neuron circuit includes a waveform generating circuit for generating an analog pulse voltage, and a switching pulse voltage which is input as a first input signal to another neural network circuit element; a synapse circuit is configured such that the analog pulse voltage generated in the neuron circuit of the neural network circuit element including the synapse circuit is input to a third terminal of a variable resistance element of the synapse circuit, for a permissible input period, in the first input signal from another neural network circuit element; and the synapse circuit is configured such that the resistance value of the variable resistance element is changed in response to an electric potential difference between a first terminal and the third terminal, which occurs depending on a magnitude of the analog pulse voltage for the permissible input period.

First claim

What is claimed is:

1. A neural network circuit including a plurality of neural network circuit elements which are interconnected,
wherein each of the plurality of neural network circuit elements includes:
at least one synapse circuit which receives as an input a first input signal output from another neural network circuit element; and
one neuron circuit which receives as an input a signal output from the at least one synapse circuit;
wherein the synapse circuit includes a variable resistance element;
wherein the variable resistance element includes a first terminal, a second terminal, and a third terminal;
wherein a resistance value between the first terminal and the second terminal changes in response to an electric potential difference between the first terminal and the third terminal;
wherein the neuron circuit includes a waveform generating circuit for generating an analog pulse voltage having a specified waveform, which is output to the synapse circuit of the neural network circuit element including the neuron circuit, and a switching pulse voltage which has a waveform with a specified duration and is input as the first input signal to the synapse circuit of the another neural network circuit element;
wherein the synapse circuit is configured such that the analog pulse voltage generated in the neuron circuit of the neural network circuit element including the synapse circuit is input to the third terminal of the variable resistance element of the synapse circuit, for a permissible input period with the specified duration, as the first input signal from the another neural network circuit element; and
wherein the synapse circuit is configured such that the resistance value of the variable resistance element is changed in response to an electric potential difference between the first terminal and the third terminal, which occurs depending on a magnitude of the analog pulse voltage for the permissible input period.

2. The neural network circuit according to claim 1 ,
wherein the plurality of neural network circuit elements are mounted on a plurality of chips; and
wherein the plurality of chips are configured such that an output terminal of at least one neural network circuit element mounted on one chip is connected to an input terminal of at least one neural network circuit element mounted on another chip.

3. The neural network circuit according to claim 1 ,
wherein the synapse circuit includes a first switch which performs switching of connection or disconnection between the third terminal of the variable resistance element and a terminal of the neuron circuit from which the analog pulse voltage is output; and
wherein the first switch performs the switching of the connection or the disconnection in response to the first input signal from the another neural network circuit element.

4. The neural network circuit according to claim 1 ,
wherein the variable resistance element is a ferroelectric gate transistor.

5. The neural network circuit according to claim 4 ,
wherein the ferroelectric gate transistor includes a control electrode provided on a substrate; a ferroelectric layer provided such that the control electrode is in contact with the ferroelectric layer, a semiconductor layer provided on the ferroelectric layer, and a first electrode and a second electrode which are provided on the semiconductor layer; and
wherein the ferroelectric gate transistor is configured such that a resistance value between the first electrode and the second electrode changes in response to an electric potential difference between the first electrode and the control electrode.

6. The neural network circuit according to claim 1 ,
wherein the neuron circuit includes:
an integrating circuit which integrates a value of a current flowing through the variable resistance element of the synapse circuit; and
the waveform generating circuit which generates a specified pulse voltage corresponding to the value of the current which is integrated by the integrating circuit.

7. The neural network circuit according to claim 1 ,
wherein the synapse circuit includes a second switch, one end of which is connected to a first reference voltage source and the other end of which is connected to the first terminal of the variable resistance element; and
wherein the second switch is configured to connect the first reference voltage source to the first terminal for a period during which the switching pulse voltage input from the another neural network circuit element is input to the second switch.

8. A method of learning in a neural network circuit including a plurality of neural network circuit elements which are interconnected,
wherein each of the plurality of neural network circuit elements includes:
at least one synapse circuit which receives as an input a first input signal output from another neural network circuit element; and
one neuron circuit which receives as an input a signal output from the at least one synapse circuit;
wherein the synapse circuit includes a variable resistance element;
wherein the variable resistance element includes a first terminal, a second terminal, and a third terminal;
wherein a resistance value between the first terminal and the second terminal changes in response to an electric potential difference between the first terminal and the third terminal;
wherein the neuron circuit includes a waveform generating circuit for generating an analog pulse voltage having a specified waveform, which is output to the synapse circuit of the neural network circuit element including the neuron circuit, and a switching pulse voltage which has a waveform with a specified duration and is input as the first input signal to the synapse circuit of the another neural network circuit element;
wherein the synapse circuit is configured such that the analog pulse voltage generated in the neuron circuit of the neural network circuit element including the synapse circuit is input to the third terminal of the variable resistance element of the synapse circuit, for a permissible input period with the specified duration, as the first input signal from the another neural network circuit element; and
wherein the synapse circuit is configured such that the resistance value of the variable resistance element is changed in response to an electric potential difference between the first terminal and the third terminal, which occurs depending on a magnitude of the analog pulse voltage for the permissible input period.

Assignees

• Panasonic Ip Man Co Ltd

Inventors

• Nishitani Yu
• Kaneko Yukihiro
• Ueda Michihito

Classifications

• G06N3/08

  Learning methods · CPC title

• G06N3/04 Primary

  Architecture, e.g. interconnection topology · CPC title

• G06N3/049 Primary

  Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs · CPC title

• G06N3/063

  using electronic means · CPC title