System, method and computer-accessible medium for facilitating logic encryption

Patent metadata

Field	Value
Publication number	US-9817980-B2
Application number	US-201414775138-A
Country	US
Kind code	B2
Filing date	Mar 14, 2014
Priority date	Mar 14, 2013
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

Exemplary systems, methods and computer-accessible mediums for encrypting at least one integrated circuit (IC) can include determining, using an interference graph, at least one location for a proposed insertion of at least one gate in or at the at least one IC, and inserting the gate(s) into the IC(s) at the location(s). The interference graph can be constructed based at least in part on an effect of the location(s) on at least one further location of the IC(s).

First claim

What is claimed is:

1. A non-transitory computer-accessible medium having stored thereon computer-executable instructions for encrypting at least one integrated circuit (“IC”), wherein, when a computer hardware arrangement executes the instructions, the computer arrangement is configured to perform procedures comprising: determining, using an analysis of a pairwise security of a plurality of key-gates, at least one particular key-gate of the plurality of key-gates to insert into least one combinational portion of the at least one IC;
inserting the at least one key-gate into the at least one combinational portion of the at least one IC in the at least one location;
wherein the at least one key-gate is configured to receive at least one input from a key stored in a secure memory; and
wherein the computer arrangement is configured to perform the analysis based on a determination of whether the at least one particular key-gate is unsensitized to at least one of (i) at least one primary output of the at least one IC or (ii) at least one pseudo-primary output of the at least one IC.

2. The computer-accessible medium of claim 1 , wherein the computer arrangement is configured to determine the at least one particular key-gate using an iterative procedure.

3. The computer-accessible medium of claim 1 , wherein the computer arrangement is configured to determine the at least one particular key-gate based on a determination of whether the at least one particular key-gate is pairwise secure with all previously-determined key-gates in the at least one IC.

4. The computer-accessible medium of claim 1 , wherein the computer arrangement is further configured to determine at least one further key-gate of the plurality of key-gate to insert into the at least one IC based on determination of whether the at least one further key-gate is pairwise secure with all previously determined key-gate in the at least one IC.

5. The computer-accessible medium of claim 1 , wherein the computer arrangement is configured determine whether the at least one particular key-gate is unsensitized to the at least one of (i) the at least one primary output of the at least one 1C or (ii) the at least one pseudo-primary output of the at least one 1C based on an initialization of the at least one further key-gate to a particular value.

6. The computer-accessible medium of claim 1 , wherein the at least one key-gate is at least one of an XOR gate or an XNOR gate.

7. A method for encrypting at least one integrated circuit (IC) comprising: determining, using an analysis of a pairwise security of a plurality of key-gates, at least one particular key-gate of the plurality of key-gates to insert into at least one combinational portion of the at least one IC; using a computer hardware arrangement, inserting the at least one particular key-gate into the at least one combinational portion of the at least one IC in the at least one location;
receiving, with the at least one key-gate, at least one input from a key stored in a secure memory; and
performing the analysis, using the computer arrangement, based on a determination of whether the at least one particular key-gate is unsensitized to at least one of (i) at least one primary output of the at least one IC or (ii) at least one pseudo-primary output of the at least one IC.

8. The method of claim 7 , further comprising determining, using the computer hardware arrangement, the at least one particular key-gate using an iterative procedure.

9. The method of claim 7 , further comprising determining, using the computer hardware arrangement, the at least one particular key-gate based on a determination of whether the at least one particular key-pate is pairwise secure with all previously-determined key-gates in the at least one IC.

10. The method of claim 7 , wherein the at least one gate is at least one of an XOR gate or an XNOR gate.

11. The method of claim 7 , further comprising, determining, using the computer arrangement, whether the at least one particular key-gate is unsensitized to the at least one of (i) the at least one primary output of the at least one 1C or (ii) the at least one pseudo-primary output of the at least one 1C based on an initialization of the at least one further key-gate to a particular value.

12. An encrypted circuit comprising: at least one key-gate which is provided in at least one combinational portion of the encrypted circuit, wherein a placement of the at least one key-gate is determined using an analysis of a pairwise security of a plurality of key-gates,
wherein the at least one key-gate is configured to receive at least one of its inputs from a key stored in a secure memory; and
wherein the analysis is based on a determination of whether the at least one particular key-gate is unsensitized to at least one of (i) at least one primary output of the at least one IC or (ii) at least one pseudo-primary output of the at least one IC.

13. The encrypted circuit of claim 12 , wherein the at least one key-gate includes at least one of an XOR gate or an XNOR gate.

14. The encrypted circuit of claim 12 , wherein the at least one key-gate is determined based on a determination of whether the at least one key-gate is pairwise secure with all previously-determined key-gates in the encrypted circuit.

Assignees

• Univ New York

Inventors

• Rajendran Jeyavijayan
• Pino Youngok
• Sinanoglu Ozgur
• Karri Ramesh

Classifications

• H04L9/002

  Countermeasures against attacks on cryptographic mechanisms (network architectures or network communication protocols for protection against malicious traffic H04L63/1441) · CPC title

• G06F30/30

  Circuit design · CPC title

• G09C1/00

  Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00) · CPC title

• G06F2115/08

  Intellectual property [IP] blocks or IP cores · CPC title

• H04L2209/04

  Masking or blinding · CPC title