Resource recovery for checkpoint-based high-availability in a virtualized environment

US9817733B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9817733-B2
Application numberUS-201113253519-A
CountryUS
Kind codeB2
Filing dateOct 5, 2011
Priority dateOct 5, 2011
Publication dateNov 14, 2017
Grant dateNov 14, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A data processing system provides checkpoint high-available for an application in a virtualized environment with reduced network demands. An application executes on a primary host machine comprising a first virtual machine. A virtualization module receives a designation from the application of a portion of the memory of the first virtual machine as purgeable memory, where the purgeable memory can be reconstructed by the application when the purgeable memory is unavailable. Changes are tracked to a processor state and to a remaining portion that is not purgeable memory and the changes are periodically forwarded at checkpoints to a secondary host machine. In response to an occurrence of a failure condition on the first virtual machine, the secondary host machine is signaled to continue execution of the application by using the forwarded changes to the remaining portion of the memory and by reconstructing the purgeable memory.

First claim

Opening claim text (preview).

What is claimed is: 1. A computer program product for resource recovery, comprising: a non-transitory computer readable storage device; and program code on the non-transitory computer readable storage device that when executed by a processor within a primary host machine comprising a first virtual machine with the processor, a memory, and an application executing on the processor that accesses the memory, the program code performs a series of functions comprising: receiving, from the application, a memory mapping of the application within the memory that comprises a plurality of regions including at least one first region and at least one second region; marking, via a mark purgeable function, the at least one second region as a purgeable memory that will not be tracked, wherein the purgeable memory can be reconstructed by the application at a second virtual machine of a secondary host machine when the purgeable memory is unavailable; in response to marking the purgeable memory, tracking the at least one first region within the memory mapping for changes; in response to stopping execution of the first virtual machine: forwarding only the changes to the at least one first region to the second virtual machine, wherein any changes to the purgeable memory are not forwarded to the secondary host machine; and in response to completing the forwarding of the changes, resuming execution of the first virtual machine; and in response to an occurrence of a failure condition on the first virtual machine: reconstructing the purgeable memory by the application at the second virtual machine; and signaling the secondary host machine to continue execution of the application using the forwarded changes to the at least one first region. 2. The computer program product of claim 1 , further comprising program code for: tracking changes to a processor state of the processor; periodically stopping execution of the first virtual machine; protecting access to the memory by setting an access code at each of a plurality of first storage locations of the memory that correspond to a second storage location to one of purgeable or non-purgeable; receiving the marking of the purgeable memory as an application program interface (API) call; in response to receiving the marking, setting the access code of the purgeable memory to purgeable for a selected first storage location that corresponds to a selected second storage location that comprises the purgeable memory; and in response to the access code being set as purgeable, preventing the purgeable memory from being forwarded to the secondary host machine when the changes to the at least one first region are forwarded to the second virtual machine. 3. The computer program product of claim 2 , further comprising program code for enabling access by the application to the purgeable memory by: receiving an access call from the application to access the purgeable memory; changing, via an auto-removal policy, the access code for the purgeable memory to locked, wherein changing the access code for the purgeable memory to locked prevents the purgeable memory from being disposed of while being accessed; executing a user function to access the purgeable memory specified by the access call; and restoring the access code for the purgeable memory to purgeable. 4. The computer program product of claim 3 , further comprising program code for providing a memory protection API that enables access to the memory and prevents direct access to the purgeable memory. 5. The computer program product of claim 3 , further comprising program code for: in response to receiving the access call, registering a recovery function for the purgeable memory; and in response to a fault that the purgeable memory is not present caused by attempting to access the purgeable memory, invoking the recovery function to instruct the secondary host machine to reconstruct the purgeable memory by the application on the secondary host machine. 6. The computer program product of claim 1 , further comprising program code for, in response to the occurrence of the failure condition, an operating system of the primary host machine signaling the secondary host machine to: continue execution of the application using the forwarded changes to the at least one first region; and instruct the application, while the purgeable memory is unavailable, to perform a reconstructing of the purgeable memory at the secondary host machine. 7. The computer program product of claim 1 , further comprising program code for, in response to the occurrence of the failure condition, a hypervisor of the primary host machine signaling the secondary host machine to: continue execution of the application using the forwarded changes to the at least one first region; and instruct the application, while the purgeable memory is unavailable, to perform a reconstructing of the purgeable memory at the secondary host machine. 8. A data processing system, comprising: a processor that executes an application on a primary host machine comprising a first virtual machine with the processor and a memory; and a virtualization module that executes on the processor to: receive, from the application, a memory mapping of the application within the memory that comprises a plurality of regions including at least one first region and at least one second region; mark, via a mark purgeable function, the at least one second region as a purgeable memory that will not be tracked, wherein the purgeable memory can be reconstructed by the application at a second virtual machine of a secondary host machine when the purgeable memory is unavailable; in response to marking the purgeable memory, track the at least one first region within the memory mapping for changes; in response to stopping execution of the first virtual machine: forward only the changes to the at least one first region to the second virtual machine, wherein any changes to the purgeable memory are not forwarded to the secondary host machine; and in response to completing the forwarding of the changes, resume execution of the first virtual machine; and in response to an occurrence of a failure condition on the first virtual machine: reconstruct the purgeable memory by the application at the second virtual machine; and signal the secondary host machine to continue execution of the application using the forwarded changes to the at least one first region. 9. The data processing system of claim 8 , wherein the virtualization module further causes the data processing system to: track changes to a processor state of the processor; periodically stop execution of the first virtual machine; protect access to the memory by setting an access code at each of a plurality of first storage locations of the memory that correspond to a second storage location to one of purgeable or non-purgeable; receive the marking of the purgeable memory as an application program interface (API) call; in response to receiving the marking, set the access code of the purgeable memory to purgeable for a selected first storage location that corresponds to a selected second storage location that comprises the purgeable memory; and in response to the access code being set as purgeable, prevent the purgeable memory from being forwarded to the secondary host machine when the changes to the at least one first region are forwarded to the second virtual machine. 10. The data processing system of claim 9 , wherein the virtualization module further causes the data processing system to enable access by the application to the purgeable memory by causing the data processing system to: receive an access call from the application to a

Assignees

Inventors

Classifications

  • where the redundant components share neither address space nor persistent storage · CPC title

  • using centralised failover control functionality · CPC title

  • Failover techniques · CPC title

  • maintaining the standby controller/processing unit updated (initialisation or re-synchronisation thereof G06F11/1658 and subgroups) · CPC title

  • the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism · CPC title

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Frequently asked questions

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What does patent US9817733B2 cover?
A data processing system provides checkpoint high-available for an application in a virtualized environment with reduced network demands. An application executes on a primary host machine comprising a first virtual machine. A virtualization module receives a designation from the application of a portion of the memory of the first virtual machine as purgeable memory, where the purgeable memory c…
Who is the assignee on this patent?
Mulcahy James, North Geraint, IBM
What technology area does this patent fall under?
Primary CPC classification G06F11/2025. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Nov 14 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).