Flash memory controller, data storage device, and flash memory control method with volatile storage restoration

Patent metadata

Field	Value
Publication number	US-9817725-B2
Application number	US-201414514733-A
Country	US
Kind code	B2
Filing date	Oct 15, 2014
Priority date	Apr 23, 2014
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

A flash memory control technique with high reliability is provided. A flash memory controller provides a volatile storage area for temporary storage of logical-to-physical address mapping data between a host and a flash memory as well as error detection codes encoded from the logical-to-physical address mapping data. When reading from the volatile storage area, the microcontroller of the flash memory controller is configured to perform an error detection procedure based on the error detection codes. The microcontroller is further configured to restore the logical-to-physical address mapping data in the volatile storage area based on a backup of the logical-to-physical address mapping data.

First claim

What is claimed is:

1. A flash memory controller, operating a flash memory in accordance with commands issued from a host, comprising:
a first volatile storage area, storing logical-to-physical address mapping data between the host and the flash memory as well as error detection codes encoded from the logical-to-physical address mapping data;
a second volatile storage area, storing firmware code downloaded from the flash memory and error checking and correction codes encoded from the firmware code read from the flash memory, wherein the error checking and correction codes encoded from the firmware code are generated in response to write operations that write the firmware code downloaded from the flash memory into the second volatile storage area; and
a microcontroller, configured to perform an error detection procedure based on the error detection codes when reading from the first volatile storage area, and configured to perform an error checking and correction procedure based on the error checking and detection codes when reading from the second volatile storage area,
wherein when the error detection procedure shows that logical-to-physical address mapping data retrieved from the first volatile storage area is incorrect, the microcontroller is configured to restore the logical-to-physical address mapping data in the first volatile storage area based on a backup of the logical-to-physical address mapping data.

2. The flash memory controller as claimed in claim 1 , wherein:
the microcontroller is configured to update the backup at a constant cycle time;
the constant cycle time depends on processing conditions of the first volatile storage area; and
a possible number of bit transitions, due to cosmic particle impact during the constant cycle time on each section of data managed by each error detection code, does not exceed error detection capability of the error detection code.

3. The flash memory controller as claimed in claim 1 , wherein the backup is stored in a non-volatile memory of the host.

4. The flash memory controller as claimed in claim 1 , wherein:
before updating the logical-to-physical address mapping data in the first volatile storage area, the microcontroller is further configured to perform the error detection procedure on the logical-to-physical address mapping data expected to be written into the first volatile storage area; and
the error detection codes are generated by an error detection module.

5. The flash memory controller as claimed in claim 1 , further comprising:
a third volatile storage area for data buffering between the host and the flash memory and being stored with error checking and correction codes encoded from buffered data,
wherein:
when reading from the third volatile storage area for the buffered data, the microcontroller is configured to perform an error checking and correction procedure based on the error checking and correction codes encoded from the buffered data; and
the error checking and correction codes encoded from the buffered data are generated by an error checking and correction module specifically for the data buffering.

6. The flash memory controller as claimed in claim 5 , further comprising:
a static random access memory, allocated to provide the first, second and third volatile storage areas.

7. A data storage device, comprising the flash memory controller as claimed in claim 1 and the flash memory.

8. A flash memory control method, operating a flash memory in accordance with commands issued from a host, comprising:
providing a first volatile storage area to store logical-to-physical address mapping data between the host and the flash memory and error detection codes encoded from the logical-to-physical address mapping data;
providing a second volatile storage area to store firmware code downloaded from the flash memory and error checking and correction codes encoded from the firmware code read from the flash memory, wherein the error checking and correction codes encoded from the firmware code are generated in response to write operations that write the firmware code downloaded from the flash memory into the second volatile storage area;
when reading from the first volatile storage area, performing an error detection procedure based on the error detection codes;
when the error detection procedure shows that logical-to-physical address mapping data retrieved from the first volatile storage area is incorrect, restoring the logical-to-physical address mapping data in the first volatile storage area based on a backup of the logical-to-physical address mapping data; and
when reading from the second volatile storage area, perform an error checking and correction procedure based on the error checking and detection codes.

9. The flash memory control method as claimed in claim 8 , further comprising:
updating the backup at a constant cycle time,
wherein:
the constant cycle time depends on processing conditions of the first volatile storage area; and
a possible number of bit transitions, due to cosmic particle impact during the constant cycle time on each section of data managed by each error detection code, does not exceed error detection capability of the error detection code.

10. The flash memory control method as claimed in claim 8 , wherein:
the backup is stored in non-volatile memory of the host.

11. The flash memory control method as claimed in claim 8 , further comprising:
before updating the logical-to-physical address mapping data in the first volatile storage area, performing the error detection procedure on the logical-to-physical address mapping data expected to be written into the first volatile storage area,
wherein the error detection codes are generated by an error detection module.

12. The flash memory control method as claimed in claim 8 , further comprising:
providing a third volatile storage area for data buffering between the host and the flash memory and further using the third volatile storage area to store error checking and correction codes encoded from buffered data; and
performing an error checking and correction procedure based on the error checking and correction codes encoded from the buffered data when reading from the third volatile storage area,
wherein the error checking and correction codes encoded from the buffered data are generated by an error checking and correction module specifically for the data buffering.

Assignees

• Via Tech Inc

Inventors

• Tsai Chin-Yin
• Lai Yi-Lin

Classifications

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F11/1451

  by selection of backup contents · CPC title

• G06F2212/7209

  Validity control, e.g. using flags, time stamps or sequence numbers · CPC title

• G06F2212/7207

  management of metadata or control data · CPC title

• G06F2212/1008

  Correctness of operation, e.g. memory ordering · CPC title