Memory controller

Patent metadata

Field	Value
Publication number	US-9817711-B2
Application number	US-201414478372-A
Country	US
Kind code	B2
Filing date	Sep 5, 2014
Priority date	Jun 13, 2011
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

An ECC circuit can operate in a plurality of error correction modes with different correcting capabilities for data stored in a memory. The ECC circuit calculates a syndrome with respect to information data in accordance with an error correction mode set by a control part and adds a syndrome of a fixed length in which dummy bits are added to the calculated syndrome, to the information data. When code data is read out, the ECC circuit performs a correction process on the code data by using the syndrome included in the code data.

First claim

What is claimed is:

1. A memory controller for controlling access to a semiconductor memory, comprising:
an error correction circuit configured to perform an error correction process in a plurality of error correction modes with different correcting capabilities for data stored in said semiconductor memory;
a control circuit configured to set an error correction mode to be applied to one page, which is designated to be a memory space for storing information data, when a host apparatus requests said memory controller to store said information data into said semiconductor memory; and
an interface configured to read said information data from and write said information data into said semiconductor memory, wherein
said error correction circuit includes:
a syndrome calculation circuit configured to calculate a temporary syndrome for said information data whose code length is a first fixed code length based on said error correction mode set by said control circuit, to generate a syndrome whose code length is a second fixed code length by adding dummy data to the temporary syndrome when the error correction mode set by the control circuit is not a mode with the highest correcting capability, and to generate a syndrome whose code length is the second fixed code length by setting the temporary syndrome to the syndrome when the code length of the temporary syndrome is equal to the second code length; and
a code data generation circuit configured to generate code data whose code length is a third fixed code length, the third fixed code length commonly used for said plurality of error correction modes, the code data including all bit data included in the information data with the first fixed code length and all bit data included in the syndrome with the second fixed code length,

said interface writes all bit data included in the code data with the third fixed code length into said designated one page of said semiconductor memory,
said error correction circuit further includes a correction processing circuit configured to perform a correction process on said code data by using said syndrome included in said code data read out from said one page of said semiconductor memory when said interface reads out said code data from said one page,
wherein said control circuit stores the plurality of pieces of correction mode information for specifying the error correction mode to be applied to said code data, and
wherein said control circuit stores a plurality of pieces of correction mode information duplicately into said code data and said control circuit specifies an error correction mode to be applied to said code data from said plurality of pieces of correction mode information when said control circuit reads out said code data.

2. The memory controller according to claim 1 , wherein
said error correction circuit further includes a detection circuit configured to detect the number of error bits included in said code data,
said control circuit includes a mode changing circuit configured to:
compare said number of error bits detected by said detection circuit with a threshold value of the number of error bits which is preset for a current error correction mode; and
change said current error correction mode to another error correction mode with a correcting capability higher than that of said current error correction mode when said number of error bits which is detected exceeds said threshold value,

said syndrome calculation circuit recalculates a syndrome with respect to said information data in accordance with said error correction mode after the error correction mode is changed, and
said interface stores said syndrome after being recalculated in said semiconductor memory.

3. The memory controller according to claim 2 , wherein
said code data generation circuit generates code data with said fixed code length again, which includes said information data, said syndrome which is recalculated, and said dummy data to be added thereto as needed, and
said interface rewrites said code data stored in said semiconductor memory with said code data which is calculated again.

4. The memory controller according to claim 2 , wherein said interface stores said syndrome which is recalculated at an address different from that of said syndrome which is already stored, in the same page.

5. The memory controller according to claim 1 , wherein
said control circuit first sets an error correction mode with the lowest correcting capability when a read request is issued for data stored in said semiconductor memory, and
said error correction circuit performs an error correction process on read data in accordance with said error correction mode with the lowest correcting capability which is set by said control circuit.

6. The memory controller according to claim 5 , wherein
said control circuit determines whether said error correction process is valid after said error correction process is performed in accordance with said error correction mode which is currently set and changes said error correction mode to an error correction mode with a correcting capability which is higher than that of said error correction mode which is currently set when said error correction process is determined to be invalid, and
said error correction circuit performs an error correction process again on said read data in accordance with said error correction mode after the error correction mode is changed by said control circuit.

7. The memory controller according to claim 6 , wherein said error correction circuit is capable of operating in error correction modes of three levels or more and sequentially changes said error correction mode to an error correction mode with a correcting capability higher than that of said error correction mode which is currently set until the error correction process is determined to be valid.

8. The memory controller according to claim 6 , wherein
said control circuit includes a generation circuit configured to generate error detecting data from data to be stored in said semiconductor memory,
said syndrome calculation circuit calculates a syndrome with respect to information data in which said error detecting data is added to said data to be stored in said semiconductor memory, and
said control circuit determines whether said error correction process performed by said error correction circuit is valid by checking whether there is any error in said information data by using said error detecting data after said error correction process is performed by said error correction circuit.

9. The memory controller according to claim 1 , wherein said control circuit holds information which records therein an error correction mode which is currently applied to each page.

10. The memory controller according to claim 1 , wherein said control circuit holds information which records therein an error correction mode which is currently applied to all pages and causes said error correction circuit to be adapted to said error correction mode common to all said pages of said semiconductor memory.

11. The memory controller according to claim 1 , wherein said fixed code length is a code length in a case where a syndrome length in an error correction mode with the highest correcting capability is added to said information data.

12. A memory controller for controlling access to a semiconductor memory, comprising:
a control circuit configured to set an error correction mode for an error correction process to be applied to data stored in said semiconductor memory;
a first interface configured to read out, from said semiconductor memory, first data stored in said semiconductor memory, the first data containing informat

Assignees

• Megachips Corp

Inventors

• Sugahara Takahiko
• Fukushita Eri

Classifications

• H03M13/3738

  with judging correct decoding · CPC title

• H03M13/05

  using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits {(H03M13/2906 takes precedence)} · CPC title

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F11/1044 Primary

  with specific ECC/EDC distribution · CPC title

• G06F11/10

  Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's · CPC title