System and technique for retrieving an instruction from memory based on a determination of whether a processor will execute the instruction

Patent metadata

Field	Value
Publication number	US-9817665-B2
Application number	US-201113077424-A
Country	US
Kind code	B2
Filing date	Mar 31, 2011
Priority date	Mar 31, 2011
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

A technique includes receiving a request from a processor to retrieve a first instruction from a memory for a staged execution pipeline. The technique includes selectively retrieving the first instruction from the memory in response to the request based on a determination of whether the processor will execute the first instruction.

First claim

What is claimed is:

1. A method comprising:
in response to a processor executing a fetch stage of a multiple stage instruction, generating a request on a system bus coupled to the processor to retrieve a first instruction from a memory for a staged execution pipeline;
receiving the request from the system bus;
based on a determination of whether the processor will execute the first instruction, selectively performing one of the following:
retrieving the first instruction from the memory and using the system bus to provide the retrieved first instruction to the processor in response to the request; and
bypassing retrieving the first instruction from the memory and using the system bus to provide a second instruction other than the first instruction to the processor in response to the request; and

selectively retrieving the first instruction from the memory based on a memory type associated with the memory.

2. The method of claim 1 , wherein the second instruction comprises a no operation instruction.

3. The method of claim 1 , further comprising determining whether the processor will execute the first instruction based on a signal provided by the processor.

4. The method of claim 3 , wherein the act of determining further comprises determining whether the processor will execute the first instruction based on whether the signal indicates the processor has executed a branch instruction.

5. An apparatus comprising:
a system bus;
a processor to provide a request to retrieve a first instruction from a memory for a staged execution pipeline in which the processor concurrently processes fetch, decode and execution stages associated with a plurality of instructions that include the first instruction; and
a controller, wherein the controller and the processor are separate agents on the system bus, the processor communicates the request to the controller using the system bus, and the controller selectively:
retrieves the first instruction from the memory and uses the system bus to provide the retrieved first instruction to the processor in response to the request; or
bypasses retrieving the first instruction from the memory and uses the system bus to provide a second instruction other than the first instruction to the processor in response to the request,

wherein the controller is further adapted to selectively retrieve the first instruction from the memory based on a memory type associated with the memory.

6. The apparatus of claim 5 , wherein the controller comprises a memory manager.

7. The apparatus of claim 5 , wherein the processor is adapted to provide a signal indicative of a previously fetched instruction currently being executed by the processor, and the controller is adapted to determine whether the processor will execute the first instruction based on the signal.

8. The apparatus of claim 5 , wherein the processor is adapted to provide a signal indicative of whether a previously fetched instruction currently being executed by the processor comprises a branch instruction, and the controller is adapted to determine whether the processor will execute the first instruction based on the signal.

Assignees

• Zavalney Paul I
• Silicon Lab Inc

Inventors

• Zavalney Paul I

Classifications

• G06F9/3804 Primary

  for branches, e.g. hedging, branch folding · CPC title

• G06F9/30076

  to perform miscellaneous control operations, e.g. NOP · CPC title

• G06F9/30054

  Unconditional branch instructions · CPC title