Hybrid memory systems for autonomous non-volatile memory save and restore operations

Patent metadata

Field	Value
Publication number	US-9817610-B1
Application number	US-201514963148-A
Country	US
Kind code	B1
Filing date	Dec 8, 2015
Priority date	Dec 8, 2015
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

An apparatus forms a memory system that is physically populated into a host. In a powered-on state, the apparatus logically connects to the host through a host memory controller configured to receive host-initiated commands. The memory system includes a command buffer coupled to the host memory controller to receive the host-initiated commands. The memory system comprises both volatile memory (e.g., RAM) and non-volatile memory (e.g., FLASH). A non-volatile memory controller (NVC) is coupled to the volatile memory, and is also coupled to the non-volatile memory. A command sequence processor that is co-resident with the NVC responds to a trigger signal by logically disconnecting from the host, then dispatching command sequences that perform successive read/write operations between the volatile memory and the non-volatile memory. The successive read/write operations are performed even when the host is in a powered-down state.

First claim

What is claimed is:

1. A memory system receiving one or more host commands from a host memory controller, the memory system comprising:
at least one command buffer coupled to the host memory controller to receive the one or more host commands from the host memory controller;
at least one non-volatile memory controller coupled to the at least one command buffer to issue one or more local commands to the at least one command buffer; and
a command sequence processor at the at least one non-volatile memory controller to issue at least one command sequence to the at least one command buffer responsive to receiving at least one trigger signal.

2. The memory system of claim 1 , further comprising a sequence processor to control execution of the at least one command sequence.

3. The memory system of claim 2 , wherein the sequence processor invokes the execution of the at least one command sequence.

4. The memory system of claim 2 , wherein the sequence processor generates an interrupt signal when the at least one command sequence has finished executing.

5. The memory system of claim 1 , further comprising a command queue to store the at least one command sequence.

6. The memory system of claim 5 , wherein the at least one command sequence is stored in the command queue responsive to a firmware update.

7. The memory system of claim 1 , wherein the at least one command sequence is selected based at least in part on a trigger source of the at least one trigger signal.

8. The memory system of claim 1 , wherein the at least one command sequence is selected based at least in part on a set of zone mapping data.

9. The memory system of claim 8 , wherein the zone mapping data characterizes a relationship between the at least one trigger signal and the at least one command sequence.

10. The memory system of claim 1 , further comprising a response buffer to store response data for access by the command sequence processor.

11. The memory system of claim 10 , wherein the response data comprises the at least one trigger signal.

12. The memory system of claim 1 , wherein the at least one command sequence comprises one or more of the one or more local commands.

13. The memory system of claim 1 , wherein the at least one command sequence is received by the at least one command buffer concurrently with at least one of the one or more host commands.

14. The memory system of claim 1 , wherein the at least one command sequence is executed asynchronously to at least one of, the one or more host commands, or one or more local responses from the at least one command buffer.

15. The memory system of claim 1 , wherein at least a portion of the at least one command sequence accesses one or more control setting registers on the at least one command buffer.

16. The memory system of claim 1 , wherein the at least one command sequence performs at least one of, a normal mode operation, a transition trigger operation, a transition clock switch operation, a data save operation, a data restore operation, a disable host command operation, a disable host clock operation, or a wait operation.

17. The memory system of claim 1 , wherein the at least one trigger signal corresponds to at least one of, power fail monitor trigger, a save event, a backup event, a restore event, a register value, or a control setting register access event.

18. The memory system of claim 1 , further comprising one or more dynamic random access memory (DRAM) devices, wherein the command sequence comprises at least one DRAM command to operate on at least one of the one or more DRAM devices.

19. The memory system of claim 1 , further comprising one or more flash memory devices.

Assignees

• Inphi Corp

Inventors

• Shallal Aws
• Kunkel Dan

Classifications

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F12/0868

  Data transfer between cache memory and other subsystems, e.g. storage devices or host systems · CPC title

• G06F2212/1056

  Simplification · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title

• G06F11/1441

  Resetting or repowering · CPC title