Non-volatile memory systems and methods of managing power of the same

Patent metadata

Field	Value
Publication number	US-9817596-B2
Application number	US-201615270513-A
Country	US
Kind code	B2
Filing date	Sep 20, 2016
Priority date	Sep 29, 2010
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

A non-volatile memory system and a method of managing the power of the same are provided. The non-volatile memory system includes a non-volatile memory configured to store a first mapping table comprising a list of a logical address and a physical address corresponding to the logical address with respect to a code region and a list of a logical address and a physical address corresponding to the logical address with respect to a general purpose (GP) region, and a controller configured to load the first mapping table from the non-volatile memory to a first memory and load the second mapping table from the non-volatile memory to a second memory. Power-up of the second memory is delayed with respect to power-up of the non-volatile memory system and the first or second memory is powered down if a condition is satisfied, so that power consumption of the non-volatile memory system is reduced.

First claim

What is claimed is:

1. A non-volatile memory system comprising:
a first memory;
a second memory;
a non-volatile memory configured to store a first mapping table; and
a controller configured to load the first mapping table from the non-volatile memory to the first memory, the second memory configured to receive a first voltage independently of the controller, and the non-volatile memory system configured to provide power to the second memory after loading the first mapping table to the first memory.

2. The non-volatile memory system of claim 1 , wherein the controller is configured to power down the second memory if the first voltage is greater than zero.

3. The non-volatile memory system of claim 1 , wherein the controller is configured to load a second mapping table from the non-volatile memory to the second memory, the second mapping table includes address information of a general purpose region (GP) region in the non-volatile memory, the GP region configured to store at least one of user data and an application program.

4. The non-volatile memory system of claim 1 , wherein the first memory is a volatile memory.

5. The non-volatile memory system of claim 1 , wherein the second memory is a dynamic random-access memory (DRAM).

6. The non-volatile memory system of claim 3 , where the first mapping table includes address information of a code region in the non-volatile memory.

7. The non-volatile memory system of claim 6 , wherein the controller is configured to process access requests and power down the second memory if the controller does not receive an access request for the GP region.

8. The non-volatile memory system of claim 6 , wherein the address information of the code region and the GP region each include a list of logical addresses and physical addresses corresponding to the logical addresses.

9. The non-volatile memory system of claim 7 , wherein the non-volatile memory is partitioned into the code region configured to store a boot code, the GP region, a first mapping table region configured to store the first mapping table, a second mapping table region configured to store the second mapping table, and a mapping manager region configured to store mapping manager information, the mapping manager information including address information of the first mapping table and address information of the second mapping table.

10. The non-volatile memory system of claim 9 , wherein the controller is configured to scan the mapping manager region in the non-volatile memory, extract the address information of the first mapping table, load the first mapping table to the first memory according to the address information of the first mapping table, read the boot code from the code region using the first mapping table, and transmit the boot code.

11. The non-volatile memory system of claim 9 , wherein the controller is configured to supply power to the second memory after the non-volatile memory system receives power, if the controller processes the access request for the GP region.

12. The non-volatile memory system of claim 11 , wherein after supplying power to the second memory, the controller is configured to scan the mapping manager information in the non-volatile memory, extract the address information of the second mapping table, and load the second mapping table to the second memory according to the address information of the second mapping table.

13. The non-volatile memory system of claim 12 , wherein after loading the second mapping table to the second memory, the controller is configured to transmit the first mapping table from the first memory to the second memory, store the first mapping table in the second memory, and power down the first memory after storing the first mapping table in the second memory.

14. The non-volatile memory system of claim 12 , wherein if the controller receives a flush command, the controller is configured to transmit the first mapping table stored in the second memory to the first memory, back up the second mapping table stored in the second memory to the non-volatile memory, and then transmit a backup completion response.

15. The non-volatile memory system of claim 12 , wherein the controller is configured to receive a standby command and the controller is configured to back up the second mapping table stored in the second memory to the non-volatile memory in response to the standby command, power down the second memory, and transmit a power-down completion response.

16. The non-volatile memory system of claim 13 , wherein the controller is configured to transmit the first mapping table stored in the second memory to the first memory, back up the second mapping table stored in the second memory to the non-volatile memory, and power down the second memory during an idle time.

17. The non-volatile memory system of claim 13 , wherein if the controller receives a flush command, the controller is configured to transmit the first mapping table stored in the second memory to the first memory, back up the second mapping table stored in the second memory to the non-volatile memory, and transmit a backup completion response.

18. The non-volatile memory system of claim 16 , wherein the controller is configured to determine the idle time if the controller does not receive a command for at least a period of time.

19. The non-volatile memory system of claim 4 , where the second memory is a volatile memory.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ju Jae-Hyeon
• Choi Young Joon
• Sohn Han Gu
• Jeong Hyo Jin

Classifications

• Y02B60/1225

  Cross-Sectional Technologies · mapped topic

• G06F2212/1028

  Power efficiency · CPC title

• G11C7/1072

  for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories · CPC title

• G06F12/0292

  using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10) · CPC title

• G06F3/0625 Primary

  Power saving in storage systems · CPC title