Impedance measuring circuit

US9817035B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9817035-B2
Application numberUS-201615065388-A
CountryUS
Kind codeB2
Filing dateMar 9, 2016
Priority dateOct 5, 2015
Publication dateNov 14, 2017
Grant dateNov 14, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An impedance measuring circuit has an amplifier connected to a target and to amplify an input AC voltage with a gain corresponding to an impedance in the target and to output the voltage, and a voltage level setting circuit to set a DC voltage level in an output node of the amplifier when a first capacitor is connected between one end of the target and an output node of the amplifier and a second capacitor is connected between another end of the target and a node with a voltage correlated with the input AC voltage.

First claim

Opening claim text (preview).

The invention claimed is: 1. An impedance measuring circuit, comprising: an amplifier connected to a target and to amplify an input AC voltage with a gain corresponding to an impedance in the target and to output the voltage; and a voltage level setting circuit to set a DC voltage level in an output node of the amplifier when a first capacitor is connected between one end of the target and an output node of the amplifier and a second capacitor is connected between another end of the target and a node with a voltage correlated with the input AC voltage. 2. The impedance measuring circuit according to claim 1 , comprising: a first resistor applied with the input AC voltage at one end thereof and connected to an input node of the amplifier at another end thereof, wherein the voltage correlated with the input AC voltage is output from the other end of the first resistor. 3. The impedance measuring circuit according to claim 1 , wherein the voltage level setting circuit equalizes a DC voltage level at the output node of the amplifier to a DC voltage level of the input AC voltage. 4. The impedance measuring circuit according to claim 1 , wherein the voltage level setting circuit feeds back a signal obtained by removing an AC component included in an output signal of the amplifier, to an input side of the amplifier. 5. The impedance measuring circuit according to claim 1 , wherein the voltage level setting circuit comprises a filter to remove a frequency component of a predetermined frequency or more included in an output voltage from the amplifier, and the amplifier adjusts a gain of the input AC voltage based on an output voltage from the filter. 6. The impedance measuring circuit according to claim 5 , wherein the predetermined frequency is a frequency lower than or equal to a frequency of the input AC voltage. 7. The impedance measuring circuit according to claim 6 , wherein the amplifier comprises: a first differential amplification circuit to output a voltage corresponding to a voltage difference between the output voltage from the filter and a reference voltage which is a DC voltage level of the input AC voltage; a second differential amplification circuit to output a voltage corresponding to a voltage difference between the voltage correlated with the input AC voltage and the reference voltage; and a third differential amplification circuit to output, from the output node of the amplifier, a voltage corresponding to a voltage difference between an output voltage from the first differential amplification circuit and an output voltage from the second differential amplification circuit. 8. The impedance measuring circuit according to claim 7 , wherein the amplifier is a differential difference amplifier comprising the first differential amplification circuit, the second differential amplification circuit, and the third differential amplification circuit. 9. The impedance measuring circuit according to claim 2 , wherein the voltage level setting circuit comprises a second resistor connected between a connection node of the first resistor, the input node of the amplifier and the second capacitor and the output node of the amplifier. 10. The impedance measuring circuit according to claim 9 , wherein a resistance value of the second resistor is set according to an impedance value of the target when a total impedance value of the target including a resistor connected in series to the target is larger than a predetermined value and is set to a fixed value when the total impedance value is less than or equal to the predetermined value. 11. The impedance measuring circuit according to claim 10 , wherein a resistance value of the second resistor is more than or equal to thirty times the impedance value of the target when the total impedance value is larger than the predetermined value. 12. The impedance measuring circuit according to claim 1 , comprising: a peak hold circuit to hold a peak value of a voltage signal between one end of the target and another end of the target to output a hold value; and an impedance calculation circuit to calculate the impedance of the target based on the hold value.

Assignees

Inventors

Classifications

  • G01R15/06Primary

    having reactive components, e.g. capacitive transformer · CPC title

  • G01R27/02Primary

    Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant (by measuring phase angle only G01R25/00) · CPC title

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What does patent US9817035B2 cover?
An impedance measuring circuit has an amplifier connected to a target and to amplify an input AC voltage with a gain corresponding to an impedance in the target and to output the voltage, and a voltage level setting circuit to set a DC voltage level in an output node of the amplifier when a first capacitor is connected between one end of the target and an output node of the amplifier and a seco…
Who is the assignee on this patent?
Toshiba Kk
What technology area does this patent fall under?
Primary CPC classification G01R15/06. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Nov 14 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).