Low power low cost temperature sensor

Patent metadata

Field	Value
Publication number	US-9816872-B2
Application number	US-201414300110-A
Country	US
Kind code	B2
Filing date	Jun 9, 2014
Priority date	Jun 9, 2014
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

Systems and methods for sensing temperature on a chip are described herein. In one embodiment, a temperature sensor comprises a first transistor having a gate, a second transistor having a gate coupled to the gate of the first transistor, and a bias circuit configured to bias the gates of the first and second transistors such that the first and second transistors operate in a sub-threshold region, and to generate a current proportional to a difference between a gate-to-source voltage of the first transistor and a gate-to-source voltage of the second transistor. The temperature sensor also comprises an analog-to-digital converter (ADC) configured to convert the current into a digital temperature reading.

First claim

What is claimed is:

1. A temperature sensor, comprising:
a first transistor having a gate;
a second transistor having a gate coupled to the gate of the first transistor;
a bias circuit configured to bias the gates of the first and second transistors wherein the first and second transistors operate in a sub-threshold region, and to generate a current proportional to a difference between a gate-to-source voltage of the first transistor and a gate-to-source voltage of the second transistor using a resistor coupled to a source of the second transistor, wherein the difference between the gate-to-source voltage of the first transistor and the gate-to-source voltage of the second transistor is applied across the resistor, and the generated current is proportional to a current flowing through the resistor; and
an analog-to-digital converter (ADC) configured to convert the current into a digital temperature reading.

2. The temperature sensor of claim 1 , wherein the ADC comprises:
an oscillator configured to convert the current into a frequency; and
a counter configured to convert the frequency into a digital count value, wherein the digital temperature reading comprises the digital count value.

3. The temperature sensor of claim 1 , wherein the generated current is approximately equal to the current flowing through the resistor.

4. The temperature sensor of claim 1 , wherein the resistor is coupled between the source of the second transistor and a ground.

5. The temperature sensor of claim 1 , wherein the first transistor comprises a first field effect transistor (FET) and the second transistor comprises a second FET.

6. The temperature sensor of claim 1 , wherein the bias circuit is configured to bias the gates of the first and second transistors such that a ratio of a current of the first transistor and a current of the second transistor is approximately constant over a temperature range.

7. The temperature sensor of claim 6 , wherein the ratio is approximately equal to one.

8. The apparatus of claim 1 , further comprising a capacitor coupled to the gates of the first and second transistors.

9. The apparatus of claim 1 , wherein the bias circuit further comprises a plurality of current mirrors each coupled to at least one of the first and second transistors.

10. The apparatus of claim 9 , wherein each of the plurality of current mirrors include a plurality of Field Effect transistors (FETs).

11. The apparatus of claim 10 , wherein:
the plurality of FETs in each of the plurality of current mirrors are configured with gate widths of a first gate width; and
the first and second transistors configured with second gates widths that are substantially larger than the first gate width;
wherein the first and second transistors operate in the sub-threshold region while the plurality of FETs in the plurality of current mirrors operate in an active region.

12. A method for sensing temperature, comprising:
biasing a gate of a first transistor and a gate of a second transistor such that the first and second transistors operate in a sub-threshold region;
generating a current proportional to a difference between a gate-to-source voltage of the first transistor and a gate-to-source voltage of the second transistor; and
converting the current into a digital temperature reading;
wherein generating the current comprises applying the difference between the gate-to-source voltage of the first transistor and the gate-to-source voltage of the second transistor across a resistor, wherein the generated current is proportional to a current flowing through the resistor.

13. The method of claim 12 , wherein converting the current into the digital temperature reading comprises:
converting the current into a frequency; and
converting the frequency into a digital count value, wherein the digital temperature reading comprises the digital count value.

14. The method of claim 12 , wherein the generated current is approximately equal to the current flowing through the resistor.

15. The method of claim 12 , wherein the first transistor comprises a first field effect transistor (FET) and the second transistor comprises a second FET.

16. The method of claim 12 , further comprising biasing the gates of the first and second transistors such that a ratio of a current of the first transistor and a current of the second transistor is approximately constant over a temperature range.

17. The method of claim 16 , wherein the ratio is approximately equal to one.

18. The method of claim 12 , further comprising:
coupling a capacitor to the gates of the first and second transistors, the capacitor causing adjustment of the biasing of the gates of the first and second transistors.

19. The method of claim 12 , wherein biasing further comprises mirroring one of more currents flowing into or out of the first and second transistors with one or more current mirrors coupled to at least one of the first and second transistors.

20. The method of claim 19 , wherein:
each of the one or more current mirrors include a plurality of Field Effect transistors (FETs) that are configured with gate widths of a first gate width;
the first and second transistors configured with second gates widths that are substantially larger than the first gate width; and
operating the first and second transistors in the sub-threshold region while operating the plurality of FETs in the one or more current mirrors in an active region due the respective gate widths.

21. An apparatus for sensing temperature, comprising:
means for biasing a gate of a first transistor and a gate of a second transistor such that the first and second transistors operate in a sub-threshold region;
means for generating a current proportional to a difference between a gate-to-source voltage of the first transistor and a gate-to-source voltage of the second transistor; and
means for converting the current into a digital temperature reading;
wherein the means for generating the current comprises means for applying the difference between the gate-to-source voltage of the first transistor and the gate-to-source voltage of the second transistor across a resistor, wherein the generated current is proportional to a current flowing through the resistor.

22. The apparatus of claim 21 , wherein the means for converting the current into the digital temperature reading comprises:
means for converting the current into a frequency; and
means for converting the frequency into a digital count value, wherein the digital temperature reading comprises the digital count value.

23. The apparatus of claim 21 , wherein the generated current is approximately equal to the current flowing through the resistor.

24. The apparatus of claim 21 , wherein the first transistor comprises a first field effect transistor (FET) and the second transistor comprises a second FET.

25. The apparatus of claim 21 , further comprising means for biasing the gates of the first and second transistors such that a ratio of a current of the first transistor and a current of the second transistor is approximately constant over a temperature range.

26. The apparatus of claim 25 , wherein the ratio is approximately equal to one.

27. The apparatus of claim 21 , further comprising:
means for adjusting the means for biasing the gate of the first transistor and the gate of the second transistor, the means for adjusting

Assignees

• Qualcomm Inc

Inventors

• Zhang Junmou
• Zhang Chuang
• Chen Nan

Classifications

• G01K15/005

  Calibration · CPC title

• G01K13/00

  Thermometers specially adapted for specific purposes · CPC title

• G01K7/015 Primary

  using microstructures, e.g. made of silicon · CPC title