Techniques for entering a low-power link state

Patent metadata

Field	Value
Publication number	US-9813998-B2
Application number	US-201113042104-A
Country	US
Kind code	B2
Filing date	Mar 7, 2011
Priority date	Jun 29, 2006
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

Techniques to cause a point-to-point link between system components to engage in a negotiation process that may lead to the link transitioning from an active state in which data may be transmitted between system components to a low power state where data may not be transmitted. The negotiation process may occur between each pair of nodes within an electronic system that are interconnected via point-to-point link. The negotiation may ensure that there are no pending transactions or transactions that may occur within an upcoming period of time. Through this negotiation each component acknowledges and agrees to transition the link to the low power state.

First claim

What is claimed is:

1. An apparatus comprising:
a physical point-to-point link within an electronic system having a cache-coherent, link-based interconnect fabric;
a first component within the electronic system coupled with a first end of the point-to-point link, the first component to transmit a request over the point-to-point link to initiate transition of the point-to-point link from an active state to a low power state, the first component to operate as a master device in a power control negotiation, wherein the point-to-point link is to be incapable of transmitting packets during the low power state; and
a second component within the electronic system coupled with a second end of the point-to-point link, the second component, in response to the request, to selectively allow or disallow the transition of the point-to-point link from the active state to the low power state, wherein the second component sends negative acknowledge (NACK) message to disallow the transition of the point-to-point link from the active state to the low power state, and further wherein the first component maintains the point-to-point link in the active state in response to the NACK message, the second component to operate as a slave device in the power control negotiation, wherein no pending transactions or subsequent transactions are to occur within an upcoming period of time.

2. The apparatus of claim 1 wherein the second component sends an acknowledge message to allow the transition of the point-to-point link from the active state to the low power state, and further wherein the first component causes the point-to-point link to enter the low power state in response to the acknowledge message.

3. The apparatus of claim 1 wherein the first component does not reissue the request message for at least a predetermined period of time after receiving the NACK message from the second component.

4. The apparatus of claim 1 further comprising:
a second physical point-to-point link within the cache-coherent, link-based interconnect fabric of the electronic system;
the first component within the electronic system coupled with a first end of the second point-to-point link, the first component to transmit a second request over the second point-to-point link to initiate transition of the second point-to-point link from an active state to a low power state; and
a third component within the electronic system coupled with a second end of the second point-to-point link, the third component, in response to the second request, to selectively allow or disallow the transition of the second point-to-point link from the active state the low power state.

5. The apparatus of claim 1 further comprising:
a second physical point-to-point link within the cache-coherent, link-based interconnect fabric of the electronic system;
a third component within the electronic system coupled with a first end of the second point-to-point link, the third component to transmit a second request over the second point-to-point link to initiate transition of the second point-to-point link from an active state to a low power state; and
the first component within the electronic system coupled with a second end of the second point-to-point link, the first component, in response to the request, to selectively allow or disallow the transition of the second point-to-point link from the active state the low power state, wherein the first component is to operate as a slave device in power control negotiation for the second point-to-point link.

6. A system comprising:
a physical point-to-point link within an electronic system having a cache-coherent, link-based interconnect fabric;
a first component within the electronic system coupled with a first end of the point-to-point link, the first component to transmit a request over the point-to-point link to initiate transition of the point-to-point link from an active state to a low power state, the first component to operate as a master device in a power control negotiation, wherein the link is to be incapable of transmitting packets during the low power state;
a second component within the electronic system coupled with a second end of the point-to-point link, the second component, in response to the request, to selectively allow or disallow the transition of the point-to-point link from the active state to the low power state, wherein the second component sends negative acknowledge (NACK) message to disallow the transition of the point-to-point link from the active state to the low power state, and further wherein the first component maintains the point-to-point link in the active state in response to the NACK message, the second component to operate as a slave device in the power control negotiation, wherein no pending transactions or subsequent transactions are to occur within an upcoming period of time; and
a dynamic random access memory coupled with the second component.

7. The system of claim 6 wherein the second component sends an acknowledge message to allow the transition of the point-to-point link from the active state to the low power state, and further wherein the first component causes the point-to-point link to enter the low power state in response to the acknowledge message.

8. The system of claim 6 wherein the first component does not reissue the request message for at least a predetermined period of time after receiving the NACK message from the second component.

9. The system of claim 6 further comprising:
a second physical point-to-point link within the cache-coherent, link-based interconnect fabric of the electronic system;
the first component within the electronic system coupled with a first end of the second point-to-point link, the first component to transmit a second request over the second point-to-point link to initiate transition of the second point-to-point link from an active state to a low power state; and
a third component within the electronic system coupled with a second end of the second point-to-point link, the third component, in response to the second request, to selectively allow or disallow the transition of the second point-to-point link from the active state the low power state.

10. The system of claim 6 further comprising:
a second physical point-to-point link within the cache-coherent, link-based interconnect fabric of the electronic system;
a third component within the electronic system coupled with a first end of the second point-to-point link, the third component to transmit a second request over the second point-to-point link to initiate transition of the second point-to-point link from an active state to a low power state; and
the first component within the electronic system coupled with a second end of the second point-to-point link, the first component, in response to the request, to selectively allow or disallow the transition of the second point-to-point link from the active state the low power state, wherein the first component is to operate as a slave device in power control negotiation for the second point-to-point link.

11. A method comprising:
transmitting a request message from a master component of an electronic system to a slave component of the electronic system having a cache-coherent, link-based interconnect fabric over a physical point-to-point link, the request to initiate transition of the point-to-point link from an active state to a low power state;
receiving a response message from the slave component with the master component, the response message being either an acknowledge (ACK) message to allow transition from the active state to the low power state or a negative acknowledge (NACK) message to disallow transition from the active state to

Assignees

• Conrad Shaun M
• Safranek Robert J
• Bilgin Selim
• Intel Corp

Inventors

• Conrad Shaun M
• Safranek Robert J
• Bilgin Selim

Classifications

• H04L1/0057

  Block codes (H04L1/0061, H04L1/0064 take precedence) · CPC title

• H04W52/48

  during retransmission after error or non-acknowledgment · CPC title

• H04W52/287

  when the channel is in stand-by · CPC title

• H04W52/28 Primary

  using user profile, e.g. mobile speed, priority or network state, e.g. standby, idle or non-transmission · CPC title

• H04L1/0061

  Error detection codes · CPC title