Transmitter circuit, semiconductor apparatus and data transmission method

Patent metadata

Field	Value
Publication number	US-9813084-B2
Application number	US-201615066900-A
Country	US
Kind code	B2
Filing date	Mar 10, 2016
Priority date	Mar 17, 2015
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

The transmitter circuit according to one embodiment includes a pulse generating circuit generating a pulse signal based on edges of input data, a first output driver outputting, based on the pulse signal, a first output pulse signal according to one of the edges to a first end of an external insulating coupling element, a second output driver outputting, based on the pulse signal, a second output pulse signal according to other one of the edges to a second end of the insulating coupling element, and an output stop circuit stopping the first and second output pulse signals from being output for a prescribed period from when a power supply voltage is turned on.

First claim

What is claimed is:

1. A transmitter circuit comprising:
a pulse generating circuit generating a pulse signal based on edges of input data;
a first output driver outputting, based on the pulse signal, a first output pulse signal according to one of the edges to a first end of an external insulating coupling element;
a second output driver outputting, based on the pulse signal, a second output pulse signal according to other one of the edges to a second end of the insulating coupling element; and
an output stop circuit stopping the first and second output pulse signals from being output for a prescribed period from when a power supply voltage is turned on,
wherein the output stop circuit includes a first capacitor element connected between a power supply and a node; and
the stop of the output of the first and second output pulse signals is released when a voltage at the node reduces below a predetermined level, wherein
the output stop circuit further includes:
a latch circuit connected between the node and a ground; and
a timer, wherein
the latch circuit lowers the voltage at the node below the predetermined level in response to a signal output from the timer.

2. The transmitter circuit according to claim 1 , wherein
the output stop circuit further includes a second capacitor element,
the latch circuit has a first storage node connected to the power supply via the first capacitor element, and has a second storage node connected to the ground via the second capacitor element,
the latch circuit retains voltages inverted from each other respectively at the first and second storage nodes, and
the latch circuit releases the stop of the output of the first and second output pulse signals by the voltages retained at the first and second storage nodes transitioning in response to the signal output from the timer.

3. The transmitter circuit according to claim 1 , wherein
the output stop circuit stops the first and second output pulse signals from being output by stopping the pulse generating circuit from generating the pulse signal for a prescribed period from when the power supply voltage is turned on.

4. A semiconductor apparatus comprising:
a transmitter circuit transmitting first and second output pulse signals based on input data;
a receiver circuit receiving the first and second output pulse signals and reconstructing the input data; and
a primary insulating coupling element and a secondary insulating coupling element electromagnetically coupling the transmitter circuit and the receiver circuit to each other, wherein
the transmitter circuit includes:
a pulse generating circuit generating a pulse signal based on edges of the input data;
a first output driver outputting, based on the pulse signal, the first output pulse signal according to one of the edges to a first end of the primary insulating coupling element;
a second output driver outputting, based on the pulse signal, the second output pulse signal according to other one of the edges to a second end of the primary insulating coupling element; and
an output stop circuit stopping the first and second output pulse signals from being output for a prescribed period from when a power supply voltage is turned on,
wherein the output stop circuit includes a first capacitor element connected between a power supply and a node; and
the stop of the output of the first and second output pulse signals is released when a voltage at the node reduces below a predetermined level, wherein
the output stop circuit further includes:
a latch circuit connected between the node and a ground; and
a timer, wherein
the latch circuit lowers the voltage at the node below the predetermined level in response to a signal output from the timer.

5. The semiconductor apparatus according to claim 4 , wherein
the output stop circuit further includes a second capacitor element,
the latch circuit has a first storage node connected to the power supply via the first capacitor element, and has a second storage node connected to the ground via the second capacitor element,
the latch circuit retains voltages inverted from each other respectively at the first and second storage nodes, and
the latch circuit releases the stop of the output of the first and second output pulse signals by the voltages retained at the first and second storage nodes transitioning in response to the signal output from the timer.

6. The semiconductor apparatus according to claim 4 , wherein
the output stop circuit stops the first and second output pulse signals from being output by stopping the pulse generating circuit from generating the pulse signal for a prescribed period from when the power supply voltage is turned on.

7. The semiconductor apparatus according to claim 4 , wherein
the primary insulating coupling element and the secondary insulating coupling element are coils respectively formed in two interconnection layers stacked in a top-bottom direction in a semiconductor chip.

Assignees

• Renesas Electronics Corp

Inventors

• Takeda Koichi
• Nagase Hirokazu
• Watanabe Shinpei

Classifications

• H10W42/60

  protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H04B5/0081

  Electricity · mapped topic

• H01L2924/16152

  Electricity · mapped topic