Apparatus for high voltage tolerant driver

US9813064B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9813064-B2
Application numberUS-201314109484-A
CountryUS
Kind codeB2
Filing dateDec 17, 2013
Priority dateDec 17, 2013
Publication dateNov 7, 2017
Grant dateNov 7, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Described is an apparatus which comprises: a first power supply; a second power supply lower than the first power supply; first and second transistors coupled in series and to be biased, the first and second transistors coupled to a pad; a first pull-up transistor coupled to the first power supply and to one of the first or second transistors; a pull-down transistor coupled to one of the first or second transistors; and a second pull-up transistor coupled to the second power supply, the pull-down transistor, and to one of the first or second transistors.

First claim

Opening claim text (preview).

We claim: 1. An apparatus comprising: a first power supply; a second power supply lower than the first power supply; first and second transistors coupled in series and coupled to a bias signal and a pad; a first pull-up transistor coupled to the first power supply and to the first transistor; a pull-down transistor coupled to the second transistor; and a second pull-up transistor coupled to the second power supply, the pull-down transistor, and to the second transistor, wherein the first pull-up transistor, the first and second transistors and the pull-down transistor form a first driver to operate in a first mode of operation, and the second pull-up transistor, the pull-down transistor and the second transistor form a second driver to operate in a second mode of operation. 2. The apparatus of claim 1 , wherein the second pull-up transistor is operable to be turned off in the first mode of operation in which the first pull-up transistor is turned on. 3. The apparatus of claim 1 , wherein the second pull-up transistor is operable to be turned on in the second mode of operation in which the first pull-up transistor is turned off. 4. The apparatus of claim 1 , wherein the first transistor and the first pull-up transistor are p-type devices. 5. The apparatus of claim 1 , wherein the second transistor and the pull-down transistor are n-type devices. 6. The apparatus of claim 1 , wherein the first power supply is substantially 3.3V and the second power supply is in the range of 0.5V to 1.2V. 7. The apparatus of claim 1 , wherein the second pull-up transistor is a p-type device. 8. The apparatus of claim 1 , wherein the first driver is a USB compliant high speed (HS) driver for lower power operation, the second driver is a USB compliant classic (CL) driver for higher power operation. 9. A driver comprising: a first pull-up transistor coupled to a first power supply, the first pull-up transistor controllable by a first pre-driver; a second pull-up transistor coupled to a second power supply, the second pull-up transistor controllable by a second pre-driver; first and second transistors coupled in series and coupled to a first bias signal and a first pad, the first and second transistors separating the first pull-up transistor from the second pull-up transistor, the first transistor coupled to the first pull-up transistor and the second transistor coupled to the second pull-up transistor; and a first pull-down transistor coupled to the second pull-up transistor, wherein the first pull-up transistor, the first and second transistors and the pull-down transistor form a first driver to operate in a first mode of operation, and the second pull-up transistor, the pull-down transistor and the second transistor form a second driver to operate in a second mode of operation. 10. The driver of claim 9 , wherein the second pull-up transistor is operable to be turned off in the first mode of operation in which the first pull-up transistor is turned on. 11. The driver of claim 9 , wherein the second pull-up transistor is operable to be turned on in the second mode of operation in which the first pull-up transistor is turned off. 12. The driver of claim 9 , wherein the first power supply is greater than the second power supply. 13. The driver of claim 9 , wherein the first pull-up transistor, second pull-up transistor, first and second transistors, and first pull-down transistor are part of a USB transmitter. 14. The driver of claim 8 further comprises: a third pull-up transistor coupled to the first power supply, the third pull-up transistor controllable by a third pre-driver; a fourth pull-up transistor coupled to the second power supply, the fourth pull-up transistor controllable by a fourth pre-driver; third and fourth transistors coupled in series and coupled to a second bias signal and a second pad, the third and fourth transistors separating the third pull-up transistor from the fourth pull-up transistor; and a second pull-down transistor coupled to the second pull-up transistor. 15. The driver of claim 14 , wherein the first and third pull-up transistors, second and fourth pull-up transistors, first, second, third, and fourth transistors, and first and second pull-down transistors are part of a differential USB transmitter. 16. The driver of claim 14 , wherein the first and second pads output differential output signals. 17. The driver of claim 9 , wherein the first power supply is substantially 3.3V and the second power supply is in the range of 0.5V to 1.2V. 18. The driver of claim 9 , wherein the first driver is a USB compliant high speed (HS) driver for lower power operation, and the second driver is a USB compliant classic (CL) driver for higher power operation. 19. A driver comprising: a first pull-up transistor coupled to a first power supply, the first pull-up transistor controllable by a first pre-driver; a second pull-up transistor coupled to a second power supply, the second pull-up transistor controllable by a second pre-driver; first and second transistors coupled in series between the first pull-up transistor and the second pull-up transistor and coupled to a first bias signal and a first pad; a first pull-down transistor coupled to the second pull-up transistor; a third pull-up transistor coupled to the first power supply, the third pull-up transistor controllable by a third pre-driver; a fourth pull-up transistor coupled to the second power supply, the fourth pull-up transistor controllable by a fourth pre-driver; third and fourth transistors coupled in series between the third pull-up transistor and the fourth pull-up transistor and coupled to a second bias signal and a second pad; and a second pull-down transistor coupled to the second pull-up transistor. 20. The driver of claim 19 , wherein the first and third pull-up transistors, second and fourth pull-up transistors, first, second, third, and fourth transistors, and first and second pull-down transistors are part of a differential USB transmitter.

Assignees

Inventors

Classifications

  • Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature {(to maintain energy constant H03K3/015)} · CPC title

  • Cross-Sectional Technologies · mapped topic

  • programmable · CPC title

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What does patent US9813064B2 cover?
Described is an apparatus which comprises: a first power supply; a second power supply lower than the first power supply; first and second transistors coupled in series and to be biased, the first and second transistors coupled to a pad; a first pull-up transistor coupled to the first power supply and to one of the first or second transistors; a pull-down transistor coupled to one of the first …
Who is the assignee on this patent?
Low Chia How, Leong Chee Seng, Ho Yick Yaw, and 1 more
What technology area does this patent fall under?
Primary CPC classification H03K19/017581. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 07 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).