System and method for inductor isolation

Patent metadata

Field	Value
Publication number	US-9813033-B2
Application number	US-201514846399-A
Country	US
Kind code	B2
Filing date	Sep 4, 2015
Priority date	Sep 5, 2014
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

An inductor isolation apparatus and method to reduce interaction between inductors on an integrated circuit.

First claim

We claim:

1. An apparatus comprising:
an integrated circuit device comprising at least two frequency selective circuits, where each frequency selective circuit comprises at least one inductor element; and
a plurality of metallization walls, wherein each metallization wall encloses a respective inductor element of the at least one inductor element and reduces mutual coupling between the inductor elements of the at least two frequency selective circuits.

2. The apparatus of claim 1 wherein each metallization wall comprises a stack of vias.

3. The apparatus of claim 1 wherein each metallization wall encompasses respective circuit elements of the frequency selective circuits.

4. The apparatus of claim 1 wherein each metallization wall encompasses respective wire bond pads used to provide power to the frequency selective circuits.

5. The apparatus of claim 1 wherein each of the at least two frequency selective circuits comprise band pass filter circuits.

6. The apparatus of claim 5 wherein the band pass filter circuits are components in an amplifier circuit.

7. The apparatus of claim 1 wherein the at least two frequency selective circuits comprise two stages of a multi-stage amplifier circuit.

8. The apparatus of claim 1 wherein center frequencies of each of the at least two frequency selective circuits are staggered.

9. The apparatus of claim 1 wherein each of the at least two frequency selective circuits comprises a transconductance circuit followed by a tunable tank circuit.

10. The apparatus of claim 9 wherein the tunable tank circuits comprise respective capacitor banks, the integrated circuit further comprising a controller circuit that is configured to adjust the respective capacitor banks to alter the respective frequency responses of the at least two frequency selective circuits.

11. The apparatus of claim 9 wherein the transconductance circuit comprises a plurality of parallel connected transconductance cells.

12. The apparatus of claim 1 wherein each of the at least two frequency selective circuits comprises a linearization circuit that provides a respective auxiliary negative conductance.

13. The apparatus of claim 12 wherein each of the linearization circuits comprises a pseudo-differential cross-coupled pair of transistors biased in a sub-threshold region.

14. The apparatus of claim 13 further comprising a controller circuit configured to adjust a sub-threshold bias voltage of transistor pairs in the linearization circuit.

15. The apparatus of claim 1 further comprising a respective buffer circuit between each of the at least two frequency selective circuits.

16. A method comprising:
adjusting the gain of a variable gain amplifier stage;
adjusting a resonant frequency and a quality factor Q of a tunable bandpass filter connected as a load to the variable gain amplifier stage, wherein the bandpass filter includes an inductor that is surrounded by a metallization wall, a cross-coupled transistor pair, and at least one cross-coupled compensation transistor pair; and,
biasing the at least one cross-coupled compensation transistor pair in a subthreshold region.

17. A method comprising:
adjusting, to a first frequency, a resonant frequency of a first low noise amplifier stage having a first variable gain amplifier stage and a first tunable bandpass filter, wherein the first tunable bandpass filter comprises a first inductor surrounded by a first metallization wall;
adjusting, to a second frequency offset from the first frequency, a resonant frequency of a second low noise amplifier stage having a second variable gain amplifier stage and a second tunable bandpass filter, wherein the second tunable bandpass filter comprises a second inductor surrounded by a second metallization wall; and
biasing cross-coupled compensation transistor pairs in each of the first tunable bandpass filter and second tunable bandpass filter in a sub-threshold region to provide a compensation transconductance in the presence of large signals.

18. The method of claim 17 wherein the first frequency and second frequency are selected in accordance with a desired channel frequency.

19. The method of claim 17 , further comprising adjusting a quality factor Q of the first and second bandpass filters to obtain a desired overall bandwidth and adjacent channel rejection ratio.

20. The method of claim 17 wherein each of the adjusting steps of the first and second bandpass filter resonant frequencies comprises:
adjusting a bias point of the cross-coupled transistors to induce an oscillation in the respective bandpass filter;
measuring the resonant frequency of the oscillation; and,
adjusting the resonant frequency of the respective bandpass filter.

Assignees

• Innophase Inc

Inventors

• Testi Nicolo
• Xu Yang

Classifications

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title

• H03F3/45183

  Long tailed pairs (H03F3/4521, H03F3/45237 take precedence) · CPC title

• H03F2200/294

  the amplifier being a low noise amplifier [LNA] · CPC title

• H03F2200/408

  the output amplifying stage of an amplifier comprising three power stages · CPC title

• H03F2203/45138

  Two or more differential amplifiers in IC-block form are combined, e.g. measuring amplifiers · CPC title