Common-mode impedance network for reducing sensitivity in oscillators

Patent metadata

Field	Value
Publication number	US-9813023-B2
Application number	US-201514970865-A
Country	US
Kind code	B2
Filing date	Dec 16, 2015
Priority date	Dec 16, 2015
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

A low-complexity differential inductor and common-mode impedance network for reducing effects of flicker noise in an oscillator output signal have been disclosed. An oscillator includes a planar conductive loop comprising a first terminal, a second terminal, and a center tap. The planar conductive loop is formed from a first conductive layer above an integrated circuit substrate. The center tap is coupled to a first power supply node. The oscillator includes a planar conductive structure extending from a first point proximate to the center tap. The planar conductive structure extends along a line of symmetry of the planar conductive loop to a second point proximate to the first terminal and the second terminal. The planar conductive structure may be formed from the first conductive layer and may be directly coupled to the center tap.

First claim

What is claimed is:

1. An oscillator comprising:
a planar conductive loop comprising a first terminal, a second terminal, and a center tap, the planar conductive loop being formed from a first conductive layer above an integrated circuit substrate; and
a planar conductive structure extending from a first point proximate to the center tap and extending along a line of symmetry of the planar conductive loop to a second point proximate to the first terminal and the second terminal,
wherein the center tap is capacitively coupled to an AC ground node using the planar conductive structure, the planar conductive structure is capacitively coupled to the center tap of the planar conductive loop, and the planar conductive structure is directly coupled to the AC ground node.

2. The oscillator as recited in claim 1 , wherein the planar conductive structure at least partially bisects the planar conductive loop.

3. The oscillator as recited in claim 1 , wherein the planar conductive structure is formed from the first conductive layer and is directly coupled to the center tap.

4. An oscillator comprising:
a planar conductive loop comprising a first terminal, a second terminal, and a center tap, the planar conductive loop being formed from a first conductive layer above an integrated circuit substrate; and
a planar conductive structure extending from a first point proximate to the center tap and extending along a line of symmetry of the planar conductive loop to a second point proximate to the first terminal and the second terminal,
wherein the first terminal is coupled to a first tank capacitor directly coupled to the planar conductive structure and the second terminal is coupled to a second tank capacitor directly coupled to the planar conductive structure.

5. The oscillator as recited in claim 4 , wherein the planar conductive structure is capacitively coupled to the center tap of the planar conductive loop.

6. The oscillator as recited in claim 5 , further comprising:
a bypass capacitor coupled between the center tap and the planar conductive structure.

7. The oscillator as recited in claim 5 , wherein the planar conductive structure is directly coupled to the AC ground node.

8. The oscillator as recited in claim 4 , wherein the planar conductive structure is capacitively coupled to the AC ground node.

9. The oscillator as recited in claim 1 , further comprising:
an additional planar conductive loop coupled to the first terminal and the second terminal, the planar conductive structure extending from a point between the first terminal and the second terminal to a second center tap of the additional planar conductive loop along the line of symmetry of the planar conductive loop and the additional planar conductive loop.

10. An oscillator comprising:
a planar conductive loop comprising a first terminal, a second terminal, and a center tap, the planar conductive loop being formed from a first conductive layer above an integrated circuit substrate; and
a planar conductive structure extending from a first point proximate to the center tap and extending along a line of symmetry of the planar conductive loop to a second point proximate to the first terminal and the second terminal,
wherein the center tap is capacitively coupled to an AC ground node using the planar conductive structure,
wherein the planar conductive structure comprises a plurality of conductive lines parallel to the line of symmetry and centered with respect to the line of symmetry.

11. The oscillator as recited in claim 10 , wherein the plurality of conductive lines includes an even number of conductive lines disposed on opposing sides of the line of symmetry.

12. The oscillator as recited in claim 11 , wherein the plurality of conductive lines includes an additional conductor coincident to the line of symmetry.

13. The oscillator as recited in claim 1 , wherein the planar conductive loop and the planar conductive structure form at least a portion of a tank circuit of the oscillator and a common-mode resonant frequency f ocm of the tank circuit is twice a differential-mode resonant frequency f odm of the tank circuit.

14. The oscillator as recited in claim 1 , wherein the planar conductive loop has a line width at least an order of magnitude thicker than a second line width of the planar conductive structure.

15. The oscillator as recited in claim 1 , wherein the planar conductive structure is formed from a second conductive layer between the first conductive layer and the integrated circuit substrate and is directly coupled to the center tap using interlayer interconnect.

16. The oscillator as recited in claim 1 , further comprising:
at least one tank capacitor coupled to at least one of the first and second terminal; and
an amplifier circuit coupled between the first and second terminal.

17. The oscillator as recited in claim 1 , further comprising:
a bypass capacitor coupled between the center tap and the planar conductive structure, the bypass capacitor having a capacitance that causes the bypass capacitor to be a short circuit for frequencies of twice a differential mode frequency of the oscillator.

18. The oscillator as recited in claim 4 , further comprising:
a bypass capacitor coupled between the center tap and the planar conductive structure, the bypass capacitor having a capacitance that causes the bypass capacitor to be a short circuit for frequencies of twice a differential mode frequency of the oscillator.

19. The oscillator as recited in claim 10 , further comprising:
a bypass capacitor coupled to the center tap using interlayer interconnect, the center tap being capacitively coupled to the AC ground node further using the bypass capacitor.

Assignees

• Silicon Lab Inc

Inventors

• Caffee Aaron J

Classifications

• H03B5/12

  active element in amplifier being semiconductor device (H03B5/14 takes precedence) · CPC title

• H03L7/0812

  and where no voltage or current controlled oscillator is used · CPC title

• H03B5/08 Primary

  with frequency-determining element comprising lumped inductance and capacitance · CPC title

• H03L1/026

  by using a memory for digitally storing correction values (H03L1/025 takes precedence) · CPC title

• H03L1/00

  Stabilisation of generator output against variations of physical values, e.g. power supply · CPC title