PFC control circuit, digital PFC circuit and the method thereof

Patent metadata

Field	Value
Publication number	US-9812950-B2
Application number	US-201514737459-A
Country	US
Kind code	B2
Filing date	Jun 11, 2015
Priority date	Jun 11, 2014
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

A digital PFC circuit with improved power factor is described. The digital PFC circuit uses a compensation current generating unit and a reference current adjust unit to eliminate the effect of a current flowing through an input capacitor to the input current, so that the input current and the input line voltage of the digital PFC circuit are controlled to be in-phase.

First claim

We claim:

1. A PFC control circuit used in a power converting system, the power converting system including an input capacitor, the power converting system configured to receive an input line voltage and generate an output voltage by controlling a power switch, the PFC control circuit comprising:
an analogue to digital unit, configured to receive a feed forward signal indicative of the input line voltage, to generate a digital voltage signal;
a cycle calculating unit, configured to receive the digital voltage signal, to calculate a cycle of the input line voltage to generate a cycle signal;
a compensation current generating unit, configured to receive the cycle signal to generate a compensation current, wherein the compensation current is complementary to a current flowing through the input capacitor;
a reference current adjust unit, configured to receive the compensation current, to execute an operation on the compensation current and an original reference current signal, to generate an adjusted reference current signal; and
a PFC controller, configured to receive the adjusted reference current signal and a current sense signal indicative of a current flowing through the power switch, to generate a logical control signal to control the power switch;
wherein the cycle calculating unit comprises:
a peak detecting module, configured to receive the digital voltage signal to detect a peak value of the digital voltage signal, and to generate a peak signal;
a threshold setting module, configured to receive the peak signal to generate a first threshold and a second threshold with close voltage levels with each other, wherein both the first threshold and the second threshold are lower than the peak signal;
a threshold detecting module, configured to receive the first threshold and the second threshold, and configured to receive the digital voltage signal, to generate a trig signal when the digital voltage signal at its right half cycle is between the first threshold and the second threshold; and
a time counter module, configured to receive the trig signal to generate the cycle signal, wherein a time interval of successive two beings between the first threshold and the second threshold of the digital voltage signal at its right half cycle is the cycle of the input line voltage.

2. The PFC control circuit of claim 1 , wherein the reference current adjust unit comprises an operation unit.

3. The PFC control circuit of claim 1 , wherein the compensation current generating unit comprises:
a quasi-sine wave amplitude calculating module, configured to calculate an amplitude D imcp according to following expression (a), wherein C represents a capacitance of the input capacitor, V r represents a root mean square of the input line voltage, f represents a frequency of the input line voltage, V adc _ ref represents a reference voltage of the analogue to digital unit, and N represents a data bit of the analogue to digital unit:

D
icmp

=

2
×
π
×
f
×
C
×

2

×

V
r

×

2
N

-
1

V

adc
⁢
_
⁢
ref

;

(
a
)

a storage module, configured to receive the amplitude and a current step n, to provide a circular function value according to following expression (b)

arccos
⁡

(

D
icmp

-
n

D
icmp

)

-

arccos
⁡

(

D
icmp

+
1
-
n

D
icmp

)

π

;

(
b
)

an operation module, configured to receive the circular function value and the cycle signal, to calculate a time interval of the current step;
a timing module, configured to receive the time interval of the current step, to generate a pulse signal after timing for the time interval of the current step;
a counting module, configured to receive the pulse signal to generate the current step; and
a subtract module, configured to receive the amplitude and the current step, to generate the compensation current by executing a subtract operation on the amplitude and the current step.

4. The PFC control circuit of claim 1 , wherein the compensation current generating unit comprises:
a saw-tooth wave amplitude calculating module, configured to generate an amplitude D icmp according to following expression (c), wherein C represents a capacitance of the input capacitor, V r represents a root mean square of the input line voltage, f represents a frequency of the input line voltage, V adc _ ref represents a

Assignees

• Chengdu Monolithic Power Sys

Inventors

• Lu Wenbin
• Lin Sicong
• Zhao Qiming
• Jiang Lijie
• Zhang Guangchao

Classifications

• H02M1/4208 Primary

  Arrangements for improving power factor of AC input · CPC title

• H02M2001/0012

  Electricity · mapped topic

• H02M1/4225

  using a non-isolated boost converter · CPC title

• Y02B70/126

  Cross-Sectional Technologies · mapped topic

• H02M1/0012

  Control circuits using digital or numerical techniques (in DC/DC converters H02M3/157, H02M3/33515; in DC-AC converters H02M7/53873) · CPC title