Distributed driving system

Patent metadata

Field	Value
Publication number	US-9812942-B2
Application number	US-201213347197-A
Country	US
Kind code	B2
Filing date	Jan 10, 2012
Priority date	Jan 10, 2012
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

A step down convertor with a distributed driving system. In one embodiment, an apparatus is disclosed that includes an inductor coupled to an output node. The apparatus also includes first and second circuits. The first circuit can transmit current to the output node via the inductor, and the second can transmit current to the output node via the inductor. The apparatus also includes a third circuit for modifying operational aspects of the first circuit or the second circuit based on a magnitude of current flowing through the inductor.

First claim

What is claimed is:

1. A DC-DC convertor comprising:
an inductor coupled to an output node;
a first circuit for transmitting current to the output node via the inductor during a pulse of a pulse width modulation (PWM) signal, wherein the first circuit comprises a first transistor for transmitting current to the output node via the inductor during the pulse of the PWM signal;
a current detector circuit for generating a signal corresponding to current flow through the first circuit during the pulse of the PWM signal;
a second circuit for transmitting current to the output node via the inductor, wherein the second circuit comprises a plurality of second transistors that vary in size, wherein the plurality of second transistors are coupled in parallel;
a third circuit for generating a multibit signal based on the signal generated by the current detector circuit, wherein each bit of the multibit signal controls a respective one of the second transistors.

2. The DC-DC convertor of claim 1 wherein each of the second transistors, when activated, is configured to transmit current to the output node via the inductor.

3. The DC-DC convertor of claim 1 wherein each of the second transistors comprises a source, a gate and a drain, wherein the gates of the second transistors vary in size.

4. The DC-DC convertor of claim 1 further comprising a pulse width modulation circuit coupled to the first circuit and configured to generate the PWM signal, wherein the first circuit is configured to transmit current to the inductor with each pulse of the PWM signal.

5. The DC-DC convertor of claim 1 wherein the plurality of second transistors are coupled in parallel between an input to the inductor and a node configured to receive a second voltage.

6. The DC-DC convertor of claim 5 wherein the first circuit comprises a plurality of transistors, including the first transistor, which are coupled in parallel between the input to the inductor and another node configured to receive an input voltage.

7. A method comprising:
a first circuit transmitting current to an output node via an inductor during a pulse of a pulse width modulation (PWM) signal, wherein the first circuit comprises a first transistor for selectively transmitting current to the output node via the inductor during the pulse of the PWM signal;
a current detector circuit generating a signal corresponding to current flow through the first circuit during the pulse of the PWM signal
a second circuit transmitting current to the output node via the inductor, wherein the second circuit comprises a plurality of second transistors that vary in size, wherein the plurality of second transistors are coupled in parallel;
a third circuit generating a multibit signal based on the signal generated by the current detector circuit, wherein each bit of the multibit signal controls a respective one of the second transistors.

8. The method of claim 7 wherein the multibit signal enables activation of one or more second transistors, wherein each of the second transistors, when activated, transmit current to the output node via the inductor.

9. The method of claim 7 further comprising:
the third circuit generating a sample current that is proportional to the current flowing through the first circuit;
the third circuit generating a sample voltage that is proportional to the sample current;
the third circuit comparing the sample voltage to each of a plurality of reference voltages;
the third circuit generating the multibit signal based on the comparison of the sample voltage to each of the plurality of reference voltages.

10. A method comprising:
a circuit generating a pulse width modulation (PWM) signal;
a first circuit transmitting current to an output node via an inductor during a pulse of the PWM signal, wherein the first circuit comprises a transistor;
a current detector circuit generating a signal indicative of current flow through the first circuit;
a second circuit transmitting current to the output node via the inductor between pulses of the PWM signal, wherein the second circuit comprises second transistors of varying sizes, wherein the second transistors are coupled in parallel between a second voltage node and the inductor;
a third circuit for generating a multibit signal based on the signal generated by the current detector circuit, wherein each bit of the multibit signal controls a respective one of the second transistors.

11. A method comprising:
a first circuit transmitting current to an output node via an inductor during first and second pulses of a square wave, wherein the first circuit comprises a first transistor for selectively transmitting current to the output node via the inductor;
a current detector circuit generating a signal indicative of current flow through the first circuit during the first pulse;
a circuit for generating a multibit signal based on the signal generated by the current detector circuit;
a second circuit transmitting current to the output node via the inductor, wherein the second circuit transmits current between the first and second pulses of the square wave, wherein the second circuit comprises second transistors each having a source, a gate and a drain, wherein the gates of the second transistors vary in size, wherein the drains of the second transistors are coupled together, and wherein the sources of the second transistors are coupled together;
wherein each bit of the multibit signal controls a respective one of the second transistors.

12. A DC-DC convertor comprising:
an inductor coupled to an output node;
a first circuit for transmitting current to the output node via the inductor during a pulse of a pulse width modulation (PWM) signal, wherein the first circuit comprises a first transistor for selectively transmitting current to the output node via the inductor;
a current detector circuit for generating a signal corresponding to current flow through the first circuit during the pulse of the PWM signal;
a second circuit for transmitting current to the output node via the inductor, wherein the second circuit comprises second transistors each having a source, a gate and a drain, wherein the gates of the second transistors vary in size, wherein the drains of the second transistors are coupled together, and wherein the sources of the second transistors are coupled together;
a third circuit for generating a multibit signal based on the signal generated by the current detector circuit, wherein each bit of the multibit signal controls a respective one of the second transistors.

13. The DC-DC convertor of claim 12 wherein the signal generated by the current detector circuit is proportional to the current flow through the first circuit during the pulse of the PWM signal.

Assignees

• Sato Tetsuo
• Kudo Ryotaro
• Ishii Hideo
• Nakano Kenichi
• Renesas Electronics America Inc

Inventors

• Sato Tetsuo
• Kudo Ryotaro
• Ishii Hideo
• Nakano Kenichi

Classifications

• H02M2001/0054

  Electricity · mapped topic

• Y02B70/1491

  Cross-Sectional Technologies · mapped topic

• H02M1/088 Primary

  for the simultaneous control of series or parallel connected semiconductor devices · CPC title

• H02M3/158

  including plural semiconductor devices as final control devices for a single load · CPC title

• H02M1/0054

  Transistor switching losses (periodically suspending operation of switching converter in low power mode H02M1/0035) · CPC title