Field effect transistor and method for manufacturing the same

US9812560B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9812560-B2
Application numberUS-201414542705-A
CountryUS
Kind codeB2
Filing dateNov 17, 2014
Priority dateJun 1, 2010
Publication dateNov 7, 2017
Grant dateNov 7, 2017

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Provided is a novel structure of a field effect transistor using a metal-semiconductor junction. The field effect transistor includes a wiring which is provided over a substrate and also functions as a gate electrode; an insulating film which is provided over the wiring, has substantially the same shape as the wiring, and also functions as a gate insulating film; a semiconductor layer which is provided over the insulating film and includes an oxide semiconductor and the like; an oxide insulating layer which is provided over the semiconductor layer and whose thickness is 5 times or more as large as the sum of the thickness of the insulating film and the thickness of the semiconductor layer or 100 nm or more; and wirings which are connected to the semiconductor layer through openings provided in the oxide insulating layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for manufacturing an electronic device, comprising steps of: forming a first conductive film over a substrate; forming a first insulating film over the first conductive film; forming a first insulating layer and a first conductive layer; forming a semiconductor layer over and in contact with the first insulating layer and a second insulating layer over the semiconductor layer; after forming the second insulating layer, etching the semiconductor layer so that the semiconductor layer does not overlap with any side edge of the first conductive layer; forming a third insulating layer over the second insulating layer; providing an opening reaching the semiconductor layer in the second insulating layer and the third insulating layer; and forming a second conductive layer covering the opening. 2. The method for manufacturing an electronic device, according to claim 1 , further comprising a step of: heating the second insulating layer at a temperature of 200° C. or higher. 3. The method for manufacturing an electronic device, according to claim 1 , wherein the second insulating layer is an oxide formed by a sputtering method. 4. The method for manufacturing an electronic device, according to claim 1 , wherein the semiconductor layer is formed so that the semiconductor layer does not cross any side edge of the first insulating layer. 5. The method for manufacturing an electronic device, according to claim 1 , wherein the second conductive layer is directly in contact with a surface of the semiconductor layer. 6. The method for manufacturing an electronic device, according to claim 1 , further comprising a step of: diffusing oxygen from the second insulating layer to the semiconductor layer, by heating the second insulating layer. 7. The method for manufacturing an electronic device, according to claim 1 , wherein the first conductive film and the first insulating film are successively formed without exposing the substrate to the air. 8. A method for manufacturing an electronic device, comprising steps of: forming a first conductive film over a substrate; forming a first insulating film over the first conductive film; forming a semiconductor film over the first insulating film; forming a second insulating film over the semiconductor film; after forming the second insulating film, etching the second insulating film, the semiconductor film, the first insulating film, and the first conductive film to form a second insulating layer, a semiconductor layer, a first insulating layer, and a first conductive layer; forming a third insulating layer over the second insulating layer; providing an opening reaching the semiconductor layer in the second insulating layer and the third insulating layer; and forming a second conductive layer covering the opening, wherein the semiconductor layer is formed so that the semiconductor layer does not overlap with any side edge of the first insulating layer. 9. The method for manufacturing an electronic device, according to claim 8 , further comprising a step of: heating the second insulating layer at a temperature of 200° C. or higher. 10. The method for manufacturing an electronic device, according to claim 8 , wherein the second insulating layer is an oxide formed by a sputtering method. 11. The method for manufacturing an electronic device, according to claim 8 , wherein the second conductive layer is directly in contact with a surface of the semiconductor layer. 12. The method for manufacturing an electronic device, according to claim 8 , further comprising a step of: diffusing oxygen from the second insulating layer to the semiconductor layer, by heating the second insulating layer. 13. The method for manufacturing an electronic device, according to claim 8 , wherein the first conductive film, the first insulating film and the semiconductor film are successively formed without exposing the substrate to the air. 14. A method for manufacturing an electronic device, comprising steps of: forming a first conductive layer over a substrate, a first insulating layer over the first conductive layer, a semiconductor layer over and in contact with the first insulating layer and a second insulating layer over the semiconductor layer; after forming the second insulating layer, etching the semiconductor layer so that the semiconductor layer does not overlap with any side edge of the first conductive layer; forming a third insulating layer over the second insulating layer; providing an opening reaching the semiconductor layer in the second insulating layer and the third insulating layer; and forming a second conductive layer covering the opening. 15. The method for manufacturing an electronic device, according to claim 14 , further comprising a step of: heating the second insulating layer at a temperature of 200° C. or higher. 16. The method for manufacturing an electronic device, according to claim 14 , wherein the second insulating layer is an oxide formed by a sputtering method. 17. The method for manufacturing an electronic device, according to claim 14 , wherein the semiconductor layer is formed so that the semiconductor layer does not cross any side edge of the first insulating layer. 18. The method for manufacturing an electronic device, according to claim 14 , wherein the second conductive layer is directly in contact with a surface of the semiconductor layer. 19. The method for manufacturing an electronic device, according to claim 14 , further comprising a step of: diffusing oxygen from the second insulating layer to the semiconductor layer, by heating the second insulating layer.

Assignees

Inventors

Classifications

  • Thermal treatments, e.g. annealing or sintering · CPC title

  • characterised by the semiconductor material · CPC title

  • within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase · CPC title

  • using physical ablation of a target, e.g. physical vapour deposition or pulsed laser deposition · CPC title

  • being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9812560B2 cover?
Provided is a novel structure of a field effect transistor using a metal-semiconductor junction. The field effect transistor includes a wiring which is provided over a substrate and also functions as a gate electrode; an insulating film which is provided over the wiring, has substantially the same shape as the wiring, and also functions as a gate insulating film; a semiconductor layer which is …
Who is the assignee on this patent?
Semiconductor Energy Lab
What technology area does this patent fall under?
Primary CPC classification H01L29/66969. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 07 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).