Bipolar junction transistor device having base epitaxy region on etched opening in DARC layer

Patent metadata

Field	Value
Publication number	US-9812445-B2
Application number	US-201514829487-A
Country	US
Kind code	B2
Filing date	Aug 18, 2015
Priority date	Dec 5, 2013
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

A method is provided of forming a bipolar transistor device. The method comprises depositing a collector dielectric layer over a substrate in a collector active region, depositing a dielectric anti-reflective (DARC) layer over the collector dielectric layer, dry etching away a base opening in the DARC layer, and wet etching away a portion of the collector dielectric layer in the base opening to provide an extended base opening to the substrate. The method further comprises performing a base deposition to form a base epitaxy region in the extended base opening and extending over first and second portions of the DARC layer that remains as a result of the dry etching away the base opening in the DARC layer, and forming an emitter region over the base epitaxy region.

First claim

What is claimed is:

1. A heterojunction bipolar transistor (HBT) transistor device comprising:
a collector dielectric layer overlying a silicon substrate in a collector active region;
a first dielectric anti-reflective (DARC) layer overlying the collector dielectric layer;
a base epitaxy region extending through a base opening through the collector dielectric layer and the first DARC layer and extending over first and second portions of the first DARC layer on opposing sides of the base opening, the base epitaxy region having a single crystal portion overlying the silicon substrate and polysilicon regions on the opposing sides of the base opening;
an emitter dielectric layer overlying the base epitaxy region;
a second DARC layer overlying the emitter dielectric layer;
a highly doped emitter material region extended though an emitter opening in contact with the single crystal portion and extending over first and second portions of the second DARC layer on opposing sides of the emitter opening;
a base contact opening extending through the highly doped emitter material region, the second DARC layer and the emitter dielectric to one or more doped regions of the base epitaxy region;
an emitter contact opening extending through the highly doped emitter material region, the second DARC layer, the emitter dielectric, the base epitaxy region, the first DARC layer, and the collector dielectric layer to a doped collector contact region in the silicon substrate; and
wherein the first DARC layer and the second DARC layer are formed from silicon-rich oxynitride layers that both function as hard masks and ant-reflective layers during photolithography and have a low dielectric constant.

2. The semiconductor structure of claim 1 , and further comprising one or more complementary metal oxide semiconductor (CMOS) devices disposed in another area of the silicon substrate.

3. The semiconductor structure of claim 1 , wherein the silicon-rich oxynitride layers have a dielectric constant of about 4.

Assignees

• Shea Patrick B
• Rennie Michael
• Di Giacomo Sandro J
• Northrop Grumman Systems Corp

Inventors

• Shea Patrick B
• Rennie Michael
• Di Giacomo Sandro J

Classifications

• H10P50/73

  using masks for insulating materials · CPC title

• H10P14/3456

  Polycrystalline · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title