Interconnect structures for assembly of multi-layer semiconductor devices

Patent metadata

Field	Value
Publication number	US-9812429-B2
Application number	US-201515312063-A
Country	US
Kind code	B2
Filing date	Nov 5, 2015
Priority date	Nov 5, 2014
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

A multi-layer semiconductor device includes a first semiconductor structure having first and second opposing surfaces, the second surface of the first semiconductor structure having at least a first semiconductor package pitch. The multi-layer semiconductor device also includes a second semiconductor structure having first and second opposing surfaces, the first surface of the second semiconductor structure having a second semiconductor package pitch. The multi-layer semiconductor device additionally includes a third semiconductor structure having first and second opposing surfaces, the first surface of the third semiconductor structure having a third semiconductor package pitch which is different from at least the second semiconductor package pitch. The second and third semiconductor structures are provided on a same package level of the multi-layer semiconductor device. A corresponding method for fabricating a multi-layer semiconductor device is also provided.

First claim

The invention claimed is:

1. A multi-layer semiconductor device comprising:
a first semiconductor structure having first and second opposing surfaces, the second surface of the first semiconductor structure having at least a first semiconductor package pitch;
a second semiconductor structure having first and second opposing surfaces, the first surface of the second semiconductor structure having a second semiconductor package pitch;
a third semiconductor structure having first and second opposing surfaces, the first surface of the third semiconductor structure having a third semiconductor package pitch which is different from at least the second semiconductor package pitch;
one or more first interconnect structures disposed between and coupled to first select portions of the first surface of the second semiconductor structure and to first select portions of the second surface of the first semiconductor structure to form an interconnect for electrically and mechanically coupling the second semiconductor structure to the first semiconductor structure, each of the first interconnect structures having first and second opposing portions, wherein a distance between the first and second portions is selected based upon at least one of the first semiconductor package pitch and the second semiconductor package pitch; and
one or more second interconnect structures disposed between and coupled to first select portions of the first surface of the third semiconductor structure and to second select portions of the second surface of the first semiconductor structure to form an interconnect for electrically and mechanically coupling the third semiconductor structure to the first semiconductor structure, each of the second interconnect structures having first and second opposing portions, wherein a distance between the first and second portions is selected based upon at least one of the first semiconductor package pitch and the third semiconductor package pitch, and the first and second interconnect structures are selected such that second semiconductor structure is provided on a same package level of the multi-layer semiconductor device as the third semiconductor structure;
wherein at least one of the first interconnect structures comprises:
a first interconnect structure portion coupled to the second surface of first semiconductor structure, including:
a first interconnect pad having first and second opposing surfaces, the first surface of the first interconnect pad corresponding to the first portion of the at least one of the first interconnect structures; and
a first conductive structure having first and second opposing surfaces and one or more sides, the first surface disposed over and coupled to the second surface of the first interconnect pad, and the second surface and select ones of the sides coated with a first fusible conductive material having a first melt temperature; and

a second interconnect structure portion coupled to the first surface of second semiconductor structure, including:
a second interconnect pad having first and second opposing surfaces, the first surface of the first interconnect pad corresponding to the second portion of the at least one of the first interconnect structures; and
a second conductive structure having first and second opposing surfaces and one or more sides, the first surface disposed over and coupled to the second surface of the second interconnect pad and wherein the second surface and select ones of the sides of the second conductive structure are coated with a second fusible conductive material having a second, different melt temperature; and

an under bump metallization (UBM) layer or structure disposed between the first surface of the second conductive structure and the second surface of the second interconnect pad, the UBM layer or structure provided from a third fusible conductive material having a third, different melt temperature.

2. The multi-layer semiconductor device of claim 1 wherein the first semiconductor structure is an interposer module or a multi-chip module (MCM).

3. The multi-layer semiconductor device of claim 1 wherein at least one of the first interconnect structures comprises:
a first interconnect structure portion coupled to the second surface of first semiconductor structure, including:
a first interconnect pad having first and second opposing surfaces, the first surface of the first interconnect pad corresponding to the first portion of the at least one of the first interconnect structures; and
a first conductive structure having first and second opposing portions, the first portion disposed over and coupled to the second surface of the first interconnect pad, and the second portion having a cavity formed in select parts of the second portion; and

a second interconnect structure portion coupled to the first surface of second semiconductor structure, including:
a second interconnect pad having first and second opposing surfaces, the first surface of the first interconnect pad corresponding to the second portion of the at least one of the first interconnect structures; and
a second conductive structure having first and second opposing portions, the first portion disposed over and coupled to the second surface of the second interconnect pad.

4. The multi-layer semiconductor device of claim 3 wherein the cavity has a predetermined shape and extends a predetermined distance between the second portion of the first conductive structure and the first portion of the first conductive structure.

5. The multi-layer semiconductor device of claim 4 wherein the predetermined shape is selected such that the cavity is shaped to receive at least a select part of the second portion of the second conductive structure during coupling.

6. The multi-layer semiconductor device of claim 3 wherein dimensions of one or more of the first interconnect pad, the first conductive structure, the cavity, the second interconnect pad and the second conductive structure are selected based upon at least one of the first semiconductor package pitch and the second semiconductor package pitch.

7. The multi-layer semiconductor device of claim 3 wherein at least one of the second portion of the second conductive structure and the cavity is coated with a fusible conductive material.

8. The multi-layer semiconductor device of claim 3 wherein the first conductive structure is provided from a material or combination of materials having a first melt temperature, and the second conductive structure is provided from a material or combination of materials having a second, different melt temperature.

9. The multi-layer semiconductor device of claim 3 wherein the second conductive structure is provided as a solder ball, sphere, pillar, or micro-bump.

10. The multi-layer semiconductor device of claim 1 wherein at least one of the second interconnect structures comprises:
a first interconnect pad coupled to the second surface of the first semiconductor structure or to the first surface of the third semiconductor structure, the first interconnect pad having first and second opposing surfaces, the first surface corresponding to the first portion of the at least one of the second interconnect structures;
a first conductive structure having first and second opposing portions and one or more edges spaced between the first and second portions, the first portion disposed over and coupled to first select portions of the second surface of the first interconnect pad, and the second portion corresponding to the second portion of the at least one of the second interconnect structures; and
a first barrier structure having first and second opposing surfaces and one or more sides, the first surface disposed

Assignees

• Massachusetts Inst Technology

Inventors

• Das Rabindra N
• Gouker Mark A
• Gouker Pascale
• Johnson Leonard M
• Johnson Ryan C

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title