Seal ring structure with a metal pad

Patent metadata

Field	Value
Publication number	US-9812409-B2
Application number	US-201514715087-A
Country	US
Kind code	B2
Filing date	May 18, 2015
Priority date	Aug 13, 2010
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

A method includes providing a substrate having a seal ring region and a circuit region, forming a seal ring structure over the seal ring region, forming a first frontside passivation layer above the seal ring structure, etching a frontside aperture in the first frontside passivation layer adjacent to an exterior portion of the seal ring structure, forming a frontside metal pad in the frontside aperture to couple the frontside metal pad to the exterior portion of the seal ring structure, forming a first backside passivation layer below the seal ring structure, etching a backside aperture in the first backside passivation layer adjacent to the exterior portion of the seal ring structure, and forming a backside metal pad in the backside aperture to couple the backside metal pad to the exterior portion of the seal ring structure. Semiconductor devices fabricated by such a method are also provided.

First claim

What is claimed is:

1. A method comprising:
forming a seal ring structure over a first side of a semiconductor substrate;
forming a first passivation layer over the first side of the semiconductor substrate;
forming a first metal pad over the first passivation layer on the first side of the semiconductor substrate, wherein the first metal pad includes a recess;
forming a second passivation layer directly on the first metal pad and within the recess;
after forming the second passivation layer directly on the first metal pad and within the recess, bonding a carrier wafer to the second passivation layer; and
forming a second metal pad over a second side of the semiconductor substrate that is opposite the first side of the semiconductor substrate
reducing a thickness of the semiconductor substrate after forming the first metal pad over the first side of the semiconductor substrate; and
after reducing the thickness of the semiconductor substrate, forming a trench through the semiconductor substrate that extends from the second side of the semiconductor substrate, through the first side of the semiconductor substrate and to the seal ring structure formed over the first side of the semiconductor substrate.

2. The method of claim 1 , further comprising removing a portion of the first passivation layer to expose a portion of the seal ring structure, and
wherein forming the first metal pad over the first side of the semiconductor substrate includes forming the first metal pad directly on the exposed portion of the seal ring structure.

3. The method of claim 1 , wherein forming the second passivation layer directly on the first metal pad and within the recess includes forming the second passivation layer directly on the first passivation layer, and
wherein a top surface of the first metal pad facing away from the semiconductor substrate physically contacts the second passivation layer and wherein an opposing bottom surface of the first metal pad facing the semiconductor substrate physically contacts the first passivation layer.

4. The method of claim 1 , wherein the first passivation layer is formed of a different material than the second passivation layer.

5. The method of claim 1 ,
wherein forming the second metal pad over the second side of the semiconductor substrate includes forming the second metal pad within the trench such that the second metal pad physically contacts the seal ring structure.

6. The method of claim 5 , further comprising forming a third passivation over the second side of the semiconductor substrate and directly on the second metal pad; and
forming a fourth passivation layer over the second side of the semiconductor substrate and directly on the third passivation layer.

7. The method of claim 1 , wherein forming the seal ring structure over the first side of the semiconductor substrate includes:
forming a first conductive layer over the first side of the semiconductor substrate;
forming a first via structure having a first width over the first conductive layer;
forming a second conductive layer over the first via structure; and
forming a second via structure having a second width over the second conductive layer, wherein the second width is different than the first width.

8. A device comprising:
a seal ring structure disposed over a first side of a semiconductor substrate, wherein the seal ring structure includes a first plurality of vertically stacked conductive elements and a second plurality of vertically stacked conductive elements, wherein the first plurality of vertically stacked conductive elements are laterally spaced apart from the second plurality of vertically stacked conductive elements by a plurality of dielectric material layers that extend laterally from the first plurality of vertically stacked conductive elements to the second plurality of vertically stacked conductive elements such that the first plurality of vertically stacked conductive elements do not overlap the second plurality of vertically stacked conductive elements;
a first passivation layer disposed over the seal ring structure;
a first metal pad disposed over the first passivation layer, the first metal pad having a recess, wherein the first metal pad extends continuously from directly over the first plurality of vertically stacked conductive elements to directly over the second plurality of vertically stacked conductive elements;
a second passivation layer disposed over the first metal pad and within the recess, wherein a top surface of the first metal pad facing away from the semiconductor substrate physically contacts the second passivation layer and wherein an opposing bottom surface of the first metal pad facing the semiconductor substrate physically contacts the first passivation layer; and
a second metal pad disposed over a second side of the semiconductor substrate that is opposite the first side of the semiconductor substrate.

9. The device of claim 8 , wherein the seal ring structure includes:
a first conductive layer disposed over the first side of the semiconductor substrate;
a first via structure having a first width disposed over and physically contacting the first conductive layer;
a second conductive layer disposed over and physically contacting the first via structure; and
a second via structure having a second width disposed over and physically contacting the second conductive layer, wherein the second width is different than the first width.

10. The device of claim 8 , further comprising a carrier wafer disposed over the second passivation layer.

11. The device of claim 8 , wherein the second metal pad extends from the second side of the semiconductor substrate to the first side of the semiconductor substrate.

12. The device of claim 8 , wherein the metal pad is formed of a first metal material and the seal ring structure is formed of a second metal material that is different than the first metal material.

13. The device of claim 8 , wherein the first passivation layer is formed of a different material than the second passivation layer.

14. The device of claim 8 , wherein the seal ring structure includes a contact that physically contacts the second metal pad.

15. A device comprising:
a seal ring structure disposed over a first side of a semiconductor substrate, wherein the seal ring structure includes a first plurality of vertically stacked conductive elements and a second plurality of vertically stacked conductive elements, wherein the first plurality of vertically stacked conductive elements are laterally spaced apart from the second plurality of vertically stacked conductive elements by a plurality of dielectric material layers that extend laterally from the first plurality of vertically stacked conductive elements to the second plurality of vertically stacked conductive elements such that the first plurality of vertically stacked conductive elements do not overlap the second plurality of vertically stacked conductive elements;
a first passivation layer disposed over the seal ring structure;
a first metal pad at least partially embedded within the first passivation layer and defining a recess, wherein the first metal pad extends continuously from directly over the first plurality of vertically stacked conductive elements to directly over the second plurality of vertically stacked conductive elements;
a second passivation layer disposed directly on the first metal pad and within the recess; and
a carrier wafer disposed over the second passivation layer.

16. The device of claim 15 , wherein the seal ring structure includes:
a first conductive lay

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Jeng-Shyan
• Yaung Dun-Nian
• Liu Jen-Cheng
• Lee Hsin-Hui
• Wang Wen-De
• Tsai Shu-Ting

Classifications

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/01951

  Changing the shapes of bond pads · CPC title

• H10W72/01953

  by etching · CPC title