Interconnect structure for semiconductor devices with multiple power rails and redundancy

Patent metadata

Field	Value
Publication number	US-9812396-B1
Application number	US-201615175495-A
Country	US
Kind code	B1
Filing date	Jun 7, 2016
Priority date	Jun 7, 2016
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

A method includes providing a starting interconnect structure for semiconductor device(s), the starting interconnect structure including a first metallization layer with a first power rail. The method further includes forming a second metallization layer over the first metallization layer with a second power rail, and directly electrically connecting the first power rail and the second power rail, the directly electrically connecting including forming metal-filled vias between the first power rail and the second power rail. The method further includes forming additional metallization layer(s) over the second metallization layer with additional power rail(s), and directly electrically connecting each of the additional power rail(s) to a power rail of a metallization layer directly below.

First claim

The invention claimed is:

1. A method, comprising:
providing a starting interconnect structure for one or more semiconductor devices, the starting interconnect structure comprising a first metallization layer with a first power rail;
forming a second metallization layer over the first metallization layer with a second power rail;
directly electrically connecting the first power rail and the second power rail;
wherein the directly electrically connecting comprises forming a plurality of metal-filled vias between the first power rail and the second power rail;
forming at least one additional metallization layer over the second metallization layer with at least one additional power rail; and
directly electrically connecting each of the at least one additional power rail to a power rail of a metallization layer directly below.

2. A method, comprising:
providing a starting interconnect structure for one or more semiconductor devices, the starting interconnect structure comprising a first metallization layer with a first power rail;
forming a second metallization layer over the first metallization layer with a second power rail;
directly electrically connecting the first power rail and the second power rail;
wherein the directly electrically connecting comprises forming a plurality of metal-filled vias between the first power rail and the second power rail; and
wherein forming the second metallization layer comprises:
forming a hard mask layer;
forming spacers on the hard mask layer;
removing portions of the hard mask layer not covered by the spacers;
forming one or more vias;
forming a plurality of trenches using the spacers; and
filling the trenches and vias with metal, each filled via electrically connected to one of the filled plurality of trenches.

3. The method of claim 2 , wherein the spacers are formed using one or more mandrel lines, one or more of the one or more mandrel lines being cut.

4. The method of claim 3 , wherein the spacers are formed around the one or more mandrel lines, and wherein the vias are formed below the mandrels.

5. The method of claim 4 , wherein forming the plurality of mandrel lines, cutting one or more thereof, forming the one or more vias and forming the plurality of trench each comprise using lithography and etching.

6. The method of claim 3 , further comprising removing one or more portions of the hard mask layer at any cut of the one or more mandrel lines.

7. The method of claim 2 , further comprising planarizing after the filling.

8. The method of claim 2 , wherein forming the spacers comprises:
forming a blanket layer of mandrel material; and
removing portions of the blanket layer of mandrel material.

Assignees

• Globalfoundries Inc

Inventors

• Stephens Jason Eugene
• Bouche Guillaume
• Narasimha Shreesh
• Justison Patrick Ryan
• Kim Byoung Youp
• Child Jr Craig Michael

Classifications

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/087

  involving multiple stacked pre-patterned masks · CPC title

• H10W20/084

  for dual-damascene structures · CPC title

• H10W20/062

  by smoothing of conductive parts, e.g. by planarisation · CPC title

• H10W20/43

  Layouts of interconnections · CPC title