Isolation device

Patent metadata

Field	Value
Publication number	US-9812389-B2
Application number	US-201615228727-A
Country	US
Kind code	B2
Filing date	Aug 4, 2016
Priority date	Oct 1, 2015
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

An isolation system, isolation device, and Integrated Circuit are disclosed. The isolation system is described to include an integrated circuit chip having a first capacitive plate, a second capacitive plate positioned with respect to the first capacitive plate to enable a capacitive coupling therebetween, an enhanced isolation layer positioned between the first capacitive the second capacitive plate that facilitates an electrical isolation between the first capacitive plate and the second capacitive plate, a first bonding wire that is in electrical communication with the second capacitive plate, and an isolation trench that at least partially circumscribes the first capacitive plate and is positioned between the first capacitive plate and the first bonding wire.

First claim

What is claimed is:

1. An isolation system, comprising:
a first circuit electrically isolated from a second circuit;
an integrated circuit chip, comprising:
a first capacitive plate electrically connected with the first circuit;
a second capacitive plate electrically connected with the second circuit and positioned with respect to the first capacitive plate to enable a capacitive coupling therebetween;
an enhanced isolation layer positioned between the first capacitive plate and the second capacitive plate that facilitates an electrical isolation between the first capacitive plate and the second capacitive plate;
a first bonding wire that is in electrical communication with the second capacitive plate; and
a second bonding wire that is in electrical communication with the first capacitive plate, wherein the first bonding wire is bonded at a different depth within the integrated circuit chip than the second bonding wire.

2. The isolation system of claim 1 , further comprising:
an isolation trench that at least partially circumscribes the first capacitive plate and that at least partially extends into the enhanced isolation layer.

3. The isolation system of claim 2 , wherein the isolation trench extends into at least 20 percent of the enhanced isolation layer.

4. The isolation system of claim 3 , wherein the isolation trench extends into no more than 66 percent of the enhanced isolation layer.

5. The isolation system of claim 1 , wherein the first bonding wire is directly connected with a bonding pad that is included as a metal layer of the integrated circuit chip, wherein the first bonding wire extends through a bottom pad opening that extends completely through the enhanced isolation layer over the bonding pad, and wherein the bonding pad is electrically connected with the second capacitive plate via one or more internal circuits of the integrated circuit chip.

6. The isolation system of claim 5 , wherein the second bonding wire extends through a top pad opening established over the first capacitive plate and wherein a depth of the top pad opening is less than a depth of the bottom pad opening.

7. The isolation system of claim 6 , wherein the top pad opening extends through at least one passivation layer that at least partially covers the first capacitive plate and wherein the bottom pad opening also extends through the at least one passivation layer.

8. The isolation system of claim 5 , wherein the first capacitive plate is part of a top most metal layer of the integrated circuit chip and wherein the second capacitive plate and the bonding pad are part of metal layer positioned below the top most metal layer in the integrated circuit chip.

9. The isolation system of claim 1 , further comprising:
a polyimide coating that at least partially fills an isolation trench provided around the first capacitive plate; and
at least one passivation layer, wherein the at least one passivation layer is sandwiched between the polyimide coating and the enhanced isolation layer.

10. An integrated circuit, comprising:
a top most metal layer;
a second top most metal layer, the second top most metal layer being electrically isolated from the top most metal layer;
an enhanced isolation layer positioned between the top most metal layer and the second top most metal layer that facilitates the electrical isolation between the top most metal layer and the second top most metal layer;
a first wire bond being connected to at least a first structure that is located on the top most metal layer; and
a second wire bond being connected to at least a second structure that is located on the second top most metal layer.

11. The integrated circuit of claim 10 , further comprising an isolation capacitor, wherein the isolation capacitor has a first capacitive plate that is located on the top most metal layer.

12. The integrated circuit of claim 11 , wherein the isolation capacitor has a second capacitive plate that is located on the second top most metal layer.

13. The integrated circuit of claim 11 , further comprising a substrate and an additional metal layer positioned adjacent to the second top most metal layer, wherein the additional metal layer is positioned between the second top most metal layer and the substrate, and wherein the isolation capacitor has a second capacitive plate that is located on the additional metal layer.

14. The integrated circuit of claim 11 , wherein the first structure is a flat metal layer that forms the first capacitive plate.

15. The integrated circuit of claim 14 , further comprising an opening configured to receive the second wire bond.

16. The integrated circuit of claim 11 , further comprising a trench that at least partially circumscribes the isolation capacitor.

17. The integrated circuit of claim 16 , wherein the trench extends at least partially into the enhanced isolation layer.

18. The integrated circuit of claim 16 , wherein the trench extends completely through the enhanced isolation layer.

19. An isolation device, comprising:
a substrate;
a first capacitive plate;
a second capacitive plate positioned with respect to the first capacitive plate to enable capacitive communications therebetween;
an enhanced isolation layer sandwiched between the first capacitive plate and the second capacitive plate thereby preventing electrical current from flowing between the first capacitive plate and the second capacitive plate;
a first bonding wire connected with the first capacitive plate;
a bonding pad in electrical communication with the second capacitive plate;
a second bonding wire connected with the bonding pad and separated from the first capacitive plate by an isolation trench; and
the second bonding wire connected with the second capacitive plate,
wherein the enhanced isolation layer covers the substrate entirely on a horizontal plane and wherein the first bonding wire and the second bonding wire are electrically isolated from one another within the isolation device.

20. The isolation device of claim 19 , wherein the bonding pad is positioned at a first distance from the substrate measuring at a direction perpendicular to the substrate, and the first capacitive plate is positioned at a second distance from the substrate measuring at the direction perpendicular to the substrate that is larger than the first distance.

Assignees

• Avago Technologies General Ip

Inventors

• Ho Dominique
• Tao Chris
• Tan Boon Keat

Classifications

• H10W72/07554

  changes in dispositions · CPC title

• H10W72/547

  Dispositions of multiple bond wires · CPC title

• H10W72/536

  the connected ends being ball-shaped · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W20/423

  Shielding layers · CPC title