BiMOS device with a fully self-aligned emitter-silicon and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9812369-B2
Application number	US-201615083774-A
Country	US
Kind code	B2
Filing date	Mar 29, 2016
Priority date	Apr 30, 2015
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

A method comprises providing a substrate of a first conductive type and a layer stack arranged on the substrate. The layer stack comprises a first isolation layer, a sacrificial layer, and a second isolation layer. The layer stack comprises a window formed in the layer stack through the second isolation layer, the sacrificial layer and the first isolation layer up to a surface region of the substrate. The method comprises providing a collector layer. The method comprises providing a base layer on the collector layer within the window of the layer stack. The method comprises providing an emitter layer or an emitter layer stack comprising the emitter layer on the base layer within the window of the layer stack. The method further comprises selectively removing the emitter layer or the emitter layer stack at least up to the second isolation layer.

First claim

The invention claimed is:

1. A method for manufacturing a bipolar junction transistor, the method comprising:
providing a substrate of a first conductive type and a layer stack arranged on the substrate, wherein the layer stack comprises a first isolation layer arranged on a surface region of the substrate, a sacrificial layer arranged on the first isolation layer and a second isolation layer arranged on the sacrificial layer, wherein the layer stack comprises a window formed in the layer stack through the second isolation layer, the sacrificial layer, and the first isolation layer up to the surface region of the substrate;
providing a collector layer of a first semi conductive type on the substrate within the window of the layer stack;
providing a base layer of a second semi conductive type on the collector layer within the window of the layer stack;
providing an emitter layer or an emitter layer stack comprising the emitter layer on the base layer within the window of the layer stack, such that an overfill of the window of the layer stack is achieved, wherein the emitter layer is of the first semi conductive type; and
selectively removing the emitter layer or the emitter layer stack at least up to the second isolation layer.

2. The method for manufacturing according to claim 1 , wherein the window formed in the layer stack comprises a trapezoidal form in at least one of a first area between the first isolation layer or a second area between the second isolation layer.

3. The method for manufacturing according to claim 1 , wherein flanks of at least one of the first isolation layer or second isolation layer facing the window of the layer stack are at least partly rounded or beveled.

4. The method for manufacturing according to claim 1 , wherein providing the emitter layer comprises growing the emitter layer on the base layer within the window of the layer stack.

5. The method for manufacturing according to claim 1 , wherein providing the emitter layer stack comprises growing the emitter layer on the base layer within the window of the layer stack and depositing a cap layer on the emitter layer.

6. The method for manufacturing according to claim 1 , wherein a spacer is provided on sidewalls of the window of the layer stack before the emitter layer or emitter layer stack is provided.

7. The method for manufacturing according to claim 1 , wherein the emitter layer or the emitter layer stack is selectively removed until an over etch of the emitter layer or emitter layer stack within the window of the layer stack is achieved, such that an upper surface region of the emitter layer or emitter layer stack is lower than an upper surface region of the second isolation layer.

8. The method for manufacturing according to claim 1 , wherein the emitter layer or the emitter layer stack is selectively removed using a dry etch process.

9. The method for manufacturing according to claim 1 , wherein at least one of the first isolation layer or the second isolation layer comprise a relative permittivity of less than 9.

10. The method for manufacturing according to claim 1 , wherein at least one of the first isolation layer or the second isolation layer comprises a first isolation sublayer having a first etch rate and a second isolation sublayer having a second etch rate different from the first etch rate.

11. The method for manufacturing according to claim 1 , wherein the first isolation layer is a first SiO2 layer, and wherein the second isolation layer is a second SiO2 layer.

12. The method for manufacturing according to claim 1 , wherein at least one of the first isolation layer or the second isolation layer is manufactured using a high density plasma process.

13. The method for manufacturing according to claim 1 , wherein the sacrificial layer is a SiN layer.

14. A method for manufacturing a BiMOS device, the method comprising:
providing a substrate of a first conductive type;
providing a MOS device on a surface region of the substrate;
providing a layer stack, wherein the layer stack is arranged on the surface region of the substrate and in a MOS region on the MOS device, wherein the layer stack comprises a first isolation layer arranged on the surface region of the substrate and in the MOS region on the MOS device, a sacrificial layer arranged on the first isolation layer and a second isolation layer arranged on the sacrificial layer, wherein the layer stack comprises, in a bipolar region different from the MOS region, a window formed in the layer stack through the second isolation layer, the sacrificial layer, and the first isolation layer up to the surface region of the substrate;
providing a collector layer of a first semi conductive type on the substrate within the window of the layer stack;
providing a base layer of a second semi conductive type on the collector layer within the window of the layer stack;
providing an emitter layer or an emitter layer stack comprising the emitter layer on the base layer within the window of the layer stack, such that an overfill of the window of the layer stack is achieved and such that the emitter layer or emitter layer stack is arranged on the second isolation layer also in the MOS region, wherein the emitter layer is of the first semi conductive type; and
selectively removing the emitter layer or the emitter layer stack at least up to the second isolation layer in the bipolar region and the MOS region.

15. The method for manufacturing according to claim 14 , wherein the emitter layer or the emitter layer stack is removed in the bipolar region and the MOS region up to the second isolation layer such that a distance between the surface region of the substrate and an upper region of the emitter layer or emitter layer stack of the bipolar region is smaller than a distance between the surface region of the substrate and an upper surface region of the sacrificial layer in the MOS region.

16. The method for manufacturing according to claim 14 , wherein the emitter layer or the emitter layer stack is removed in the bipolar region and the MOS region up to the second isolation layer without removing the layer stack in the MOS region.

17. The method for manufacturing according to claim 14 , wherein the layer stack is provided on the surface region of the substrate and on the MOS device such that a leveling of the second isolation layer caused by the MOS device comprises a maximum inclination of 30° relative to the surface region of the substrate.

18. The method for manufacturing according to claim 1 , wherein at least one of the first isolation layer or the second isolation layer comprise a relative permittivity of less than 7.

19. The method for manufacturing according to claim 1 , wherein at least one of the first isolation layer or the second isolation layer is a SiO 2 layer manufactured using a high density plasma process.

20. The method of manufacturing according to claim 1 , wherein the layer stack comprises a mask layer arranged on the second isolation layer,
the window being formed in the layer stack through the mask layer.

21. The method of manufacturing according to claim 20 , wherein the mask layer is a SiN layer.

22. The method of manufacturing according to claim 20 , wherein the mask layer is a carbon layer.

23. The method of manufacturing according to claim 20 , wherein the mask layer is manufactured using chemical vapor deposition.

24. The method of manufacturing according to claim 20 , further compr

Assignees

• Infineon Technologies Ag

Inventors

• Hoffmann Frank
• Manger Dirk
• Pribil Andreas
• Probst Marc
• Tegen Stefan

Classifications

• H10D84/401

  Combinations of FETs or IGBTs with BJTs · CPC title

• H01L29/0692

  Electricity · mapped topic

• H01L29/0817

  Electricity · mapped topic

• H01L21/8249 Primary

  Electricity · mapped topic

• H01L29/1004

  Electricity · mapped topic