Method of fabricating semiconductor device with an overlay mask pattern

Patent metadata

Field	Value
Publication number	US-9812364-B2
Application number	US-201615184315-A
Country	US
Kind code	B2
Filing date	Jun 16, 2016
Priority date	Oct 28, 2015
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

The disclosure relates to methods of fabricating semiconductor devices. A method of fabricating a semiconductor device is provided as follows. A target layer is formed. A hard mask layer is formed on the target layer. The hard mask layer is patterned to form an overlay mask pattern including a first mask pattern and a plateau-shaped mask pattern. The first mask pattern encloses the plateau-shaped mask pattern. The first mask pattern is spaced apart from the plateau-shaped mask pattern. The target layer is patterned using the overlay mask pattern to form a redundant fin and a plateau-shaped overlay mark. The redundant fin is removed.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, comprising:
forming a target layer;
forming a hard mask layer on the target layer;
patterning the hard mask layer to form an overlay mask pattern including a first mask pattern and a plateau-shaped mask pattern, wherein the first mask pattern encloses the plateau-shaped mask pattern and the first mask pattern is spaced apart from the plateau-shaped mask pattern;
patterning the target layer using the overlay mask pattern to form a redundant fin and a plateau-shaped overlay mark; and
removing the redundant fin.

2. The method of claim 1 ,
wherein the redundant fin is patterned using the first mask pattern, and
wherein the plateau-shaped overlay mark is patterned using the plateau-shaped mask pattern.

3. The method of claim 1 ,
wherein the hard mask layer is formed of silicon nitride, and
wherein the target layer is formed of silicon or Si x Ge 1-x , where x is a positive real number less than 1.

4. The method of claim 1 , further comprising:
forming a lower mandrel on the hard mask layer, before the patterning of the hard mask layer,
wherein the forming of the lower mandrel comprises:
forming a lower mandrel layer (silicon layer) on the hard mask layer;
patterning the lower mandrel layer to form the lower mandrel including a first lower mandrel and a second lower mandrel, wherein the first lower mandrel and the second lower mandrel are ring-shaped and concentric so that a first gap is formed between the first lower mandrel and the second lower mandrel, and wherein the second lower mandrel is positioned within the first lower mandrel and spaced apart from each other at a first distance.

5. The method of claim 4 , further comprising:
forming an upper mandrel on the lower mandrel layer, before the patterning of the lower mandrel layer,
wherein the forming of the upper mandrel comprises:
forming an upper mandrel layer (amorphous silicon layer) on the lower mandrel layer;
patterning the upper mandrel layer to form the upper mandrel including a first upper mandrel and a second upper mandrel, wherein the first upper mandrel is ring-shaped and the second upper mandrel is cross-hair shaped, wherein the first upper mandrel encloses the second upper mandrel, and wherein the first upper mandrel and the second upper mandrel are concentric so that a second gap is formed between the first upper mandrel and the second upper mandrel.

6. The method of claim 5 , further comprising:
forming a preliminary upper mask layer so that the preliminary upper mask layer conformally covers the first upper mandrel and the second upper mandrel without filling the second gap;
performing an anisotropic etching process on the preliminary upper mask layer to form a plurality of upper mask patterns, wherein each upper mask pattern is disposed on a sidewall of each of the first upper mandrel and the second upper mandrel; and
removing the first upper mandrel and the second upper mandrel after the performing of the anisotropic etching process,
wherein the upper mask patterns are spaced apart from each other, and
wherein the patterning of the lower mandrel layer is performed using the upper mask patterns.

7. The method of claim 5 ,
wherein the upper mandrel layer is formed of amorphous carbon.

8. The method of claim 4 ,
wherein the lower mandrel layer is formed of silicon.

9. The method of claim 4 , further comprising:
forming a preliminary lower mask layer (an oxide layer) on the first lower mandrel and the second lower mandrel so that the preliminary lower mask layer completely fills the first gap;
performing an anisotropic etching process on the preliminary lower mask layer to form a lower mask pattern including a first lower mask pattern, a second lower mask pattern and a third lower mask pattern, wherein the second lower mask pattern is positioned within the first gap and completely fills the first gap, wherein the first lower mask pattern is formed on an outer sidewall of the first lower mandrel, and wherein the third lower mask pattern is formed on an inner sidewall of the second lower mandrel; and
removing the lower mandrel,
wherein the first lower mask pattern, the second lower mask pattern and the third lower mask pattern are spaced apart from each other.

10. The method of claim 9 ,
wherein the first lower mask pattern, the second lower mask pattern and the third lower mask pattern are ring-shaped and concentric, and
wherein the second lower mask pattern is positioned between the first lower mask pattern and the third lower mask pattern.

11. The method of claim 9 ,
wherein the preliminary lower mask layer is formed of silicon oxide.

12. The method of claim 9 , further comprising:
forming an organic planarizing layer (OPL) so that the OPL completely covers the third lower mask pattern and partially covers the second lower mask pattern,
wherein a sidewall of the OPL is positioned on an upper surface of the second lower mask pattern, and
wherein the OPL has a first thickness.

13. The method of claim 12 ,
wherein the patterning of the hard mask layer is performed by an etching process using the first lower mask pattern, the second lower mask pattern and the OPL as an etch mask,
wherein the first lower mask pattern is used to form the first mask pattern, and
wherein a combined mask structure of the second lower mask pattern and the OPL is used to form the plateau-shaped mask pattern.

14. The method of claim 1 ,
wherein an upper surface of the redundant fin and an upper surface of the plateau-shaped overlay mark are substantially coplanar.

15. A method of forming a semiconductor device, comprising:
forming a target layer to be patterned to be a plateau-shaped overlay mark and a plurality of active fins;
forming a hard mask layer on the target layer;
forming a silicon layer on the hard mask layer;
patterning the silicon layer to form a plurality of line-shaped silicon patterns and a first ring-shaped silicon pattern and a second ring-shaped silicon pattern, wherein the line-shaped silicon patterns are spaced apart from each other at a first distance and the first ring-shaped silicon pattern is spaced apart from the second ring-shaped silicon pattern at a second distance smaller than the first distance;
forming an oxide layer on the line-shaped silicon patterns, the first ring-shaped silicon pattern and the second ring-shaped silicon pattern so that the oxide layer completely fills a gap between the first-ring shaped silicon pattern and the second ring-shaped silicon pattern;
performing an anisotropic etching process on the oxide layer to form a plurality of line-shaped oxide patterns and a first ring-shaped oxide pattern, a second ring-shaped oxide pattern and a third ring-shaped oxide pattern,
wherein the line-shaped oxide patterns are formed on sidewalls of the line-shaped silicon patterns,
wherein the first ring-shaped oxide pattern is formed on an outer sidewall of the first ring-shaped silicon pattern,
wherein the second ring-shaped oxide pattern is formed between an inner sidewall of the first ring-shaped silicon pattern and an outer sidewall of the second ring-shaped silicon pattern and completely fills the gap between the first ring-shaped silicon pattern and the second ring-shaped silicon pattern, and
wherein the third ring-shaped oxide pattern is formed on an inner sidewall of the second ring-shaped silicon pattern;

removing the line-shaped silicon patterns, the first ring-shaped silicon pattern and the second ring-shaped silicon pattern;
forming an organic planarizing layer (OPL) so that a sid

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jong-Su

Classifications

• H10P95/06

  Planarisation of inorganic insulating materials · CPC title

• H10P50/695 Primary

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title