Simulation of system designs

Patent metadata

Field	Value
Publication number	US-9811618-B1
Application number	US-201313788189-A
Country	US
Kind code	B1
Filing date	Mar 7, 2013
Priority date	Mar 7, 2013
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

A method is provided for simulating a program executable by a processor and a circuit design configured to communicate with the processor. A processor on a programmable IC is configured to execute the program. Programmable resources on the programmable IC are configured to implement a plurality of interface circuits. Each of the interface circuits is configured to communicate data between the processor and a simulation environment using a respective communication protocol. The interface circuits that uses a communication protocol used by the circuit design is enabled and other ones of the interface circuits are disabled. The circuit design is simulated in a simulation environment coupled to the programmable IC. During the simulating, the program is executed on the processor and data is communicated between the processor and the computing platform using the determined one of the plurality of interface circuits.

First claim

What is claimed is:

1. A method for simulating operation of a system design including a program executable by a processor on a programmable IC and a circuit implemented by programmable resources on the programmable IC, the circuit being configured to communicate with the program executing on the processor via an interface circuit that uses a first communication protocol, the method comprising:
configuring a processor on the programmable IC to execute the program;
configuring programmable resources on the programmable IC with a configuration data stream;
wherein the configuration data stream is configured to implement a plurality of alternative interface circuits together using the programmable resources;
wherein each of the plurality of alternative interface circuits is configured to use a respective communication protocol to communicate data between the processor and a simulation environment over a set of communication channels, and the plurality of alternative interface circuits includes an interface circuit that uses the first communication protocol;
determining and selecting by the simulation environment, one of the plurality of alternative interface circuits that is configured to use the first communication protocol based on metadata included with the plurality of alternative interface circuits and the system design;
enabling the determined one of the plurality of alternative interface circuits and disabling other ones of the plurality of alternative interface circuits after configuring the programmable IC with the configuration data stream;
simulating the circuit of the system design using the simulation environment on a computing platform coupled to the programmable IC; and
during the simulating, executing the program on the processor and communicating data between the processor and the computing platform via the determined one of the plurality of alternative interface circuits.

2. The method of claim 1 , further comprising:
during the simulating, providing a first clock signal from the computing platform to the programmable IC;
wherein the enabling of the determined one of the plurality of alternative interface circuits includes:
providing the first clock signal to the determined one of the plurality of alternative interface circuits; and
preventing the first clock signal from being provided to the other ones of the plurality of alternative interface circuits.

3. The method of claim 2 , further comprising:
providing a second clock signal from a hardware platform coupled to the programmable IC to the processor on the programmable IC, the first clock signal being unsynchronized from the second clock signal.

4. The method of claim 1 , wherein the communicating of the data between the computing platform and the programmable IC is performed over a communication channel utilizing a handshaking protocol.

5. The method of claim 4 , wherein:
the program includes one or more debug breakpoints; and
the processor is configured to, in response to executing an instruction of the program that accesses the circuit of the system design simulated using the simulation environment circuit:
communicate a transaction request message to a timer of the computing platform via the handshaking protocol; and
halt execution of the program until a message indicating the requested transaction has completed is received from the computing platform.

6. The method of claim 1 , further comprising:
during the simulating, communicating the data between the computing platform and the programmable IC over a high bit-rate communication channel.

7. The method of claim 1 , further comprising:
retrieving the configuration data stream from a database.

8. The method of claim 1 , further comprising:
compiling a circuit design specified in an IP-core to generate the configuration data stream.

9. The method of claim 1 , further comprising:
debugging the program executing on the processor during simulation using one or more debug breakpoints in the program.

10. The method of claim 1 , further comprising:
debugging the circuit of the system design simulated in the simulation environment using one or more debug breakpoints in the simulation of the circuit.

11. The method of claim 1 , wherein:
the programmable IC includes a plurality of communication ports;
the communicating of the data between the programmable IC communicates data between a subset of the plurality of communication ports; and
the simulation environment includes an address translation module configured to perform address translation between ports of the simulated circuit and ports of the programmable IC.

12. The method of claim 11 , wherein the address translation module is configured to:
communicate data output from ports of the simulated circuit, which correspond to the subset of the plurality of communication ports; and
discard data output from ports of the simulated circuit, which correspond to communication ports of the programmable IC that are not included in the subset of the plurality of communication ports.

13. A system for co-simulation of a design including a program executable by a processor and a circuit configured to communicate with the processor via an interface circuit that uses a first communication protocol, comprising:
a programmable integrated circuit (IC) including a processor and programmable resources; and
a computing platform coupled to the programmable IC;
wherein the computing platform is configured to:
configure the processor on the programmable IC to execute the program of the design;
configure the programmable resources on the programmable IC with a configuration data stream;
wherein the configuration data stream is configured to implement a plurality of alternative interface circuits together using the programmable resources;
wherein each of the plurality of alternative interface circuits is configured to use a respective communication protocol to communicate data between the processor of the programmable IC and a simulation environment executed on the computing platform over a set of communication channels, and the plurality of alternative interface circuits includes an interface circuit that uses the first protocol;
determine and select by the simulation environment, one of the plurality of alternative interface circuits that is configured to use the first communication protocol based on metadata included with the plurality of alternative interface circuits and the design;
enable the determined one of the plurality of alternative interface circuits and disable other ones of the plurality of alternative interface circuits after configuring the programmable IC with the configuration data stream; and
using the simulation environment, simulate the circuit of the design, and during the simulation, communicate data between the processor and the simulation environment using the determined one of the plurality of alternative interface circuits.

14. The system of claim 13 , wherein the computing platform is further configured to:
provide a first clock signal to the programmable IC during the simulation of the circuit of the design; and
enable the determined one of the plurality of alternative interface circuits by providing the first clock signal to the determined one of the plurality of alternative interface circuits and preventing the first clock signal from being provided to the other ones of the plurality of alternative interface circuits.

15. The system of claim 13 , wherein the simulation environment and the programmable IC are configured to communicate simulation and debugging data signals between the co

Assignees

• Xilinx Inc

Inventors

• Parekh Umang
• Sundararajan Arvind
• Dutta Sandeep

Classifications

• G06F15/7867

  with reconfigurable architecture · CPC title

• G06F30/34

  for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F30/367 Primary

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G06F17/5036 Primary

  Physics · mapped topic

• G06F17/5054

  Physics · mapped topic