Utilizing computing resources under a disabled processor node without fully enabling the disabled processor node

Patent metadata

Field	Value
Publication number	US-9811345-B2
Application number	US-201514688012-A
Country	US
Kind code	B2
Filing date	Apr 16, 2015
Priority date	Apr 16, 2015
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

Utilizing computing resources under a disabled processor node, including: identifying a disabled processor node, the disabled processor node representing a computer processor that is not being utilized for general purpose computer program instruction execution; identifying one or more computing resources that can be accessed only by the disabled processor node; and enabling a portion of the disabled processor node required to access the one or more computing resources.

First claim

What is claimed is:

1. A method comprising:
by first program instructions on a first computing device of a computing system,
identifying a disabled processor node in the computing system, wherein the disabled processor node is installed, functional, and unutilized;
identifying one or more computing resources in the computing system that can be accessed only by the disabled processor node while the disabled processor node is enabled in the computing system; and
enabling one or more components of the disabled processor node required to access the one or more computing resources by enabling certain components including a memory controller of the disabled processor node without fully enabling the entire disabled processor node and without notifying an operating system of the computing system that any component of the disabled processor node in the computing system is enabled; and
wherein enabling the one or more components of the disabled processor node that is required to access the one or more computing resources includes preventing an entry for the disabled processor node from being added to a data structure that identifies all active devices in the computing system.

2. The method of claim 1 further comprising presenting, to the operating system of the computing system, the one or more computing resources that can be accessed only by the disabled processor node.

3. The method of claim 2 wherein presenting, to the operating system of the computing system, the one or more computing resources that can be accessed only by the disabled processor node further includes adding an entry for the one or more computing resources that can be accessed only by the disabled processor node to the data structure that identifies all active devices in the computing system.

4. The method of claim 1 further comprising:
receiving a request for capacity-on-demand, the request for capacity-on-demand requesting additional computing resources in the computing system; and
in response to receiving the request for capacity-on-demand, enabling the one or more components of the disabled processor node required to access the additional computing resources.

5. The method of claim 1 wherein the one or more computing resources that can be accessed only by the disabled processor node in the computing system include one of more dual in-line memory modules (‘DIMMs’).

6. An apparatus comprising:
a computer processor of a computing system; and
a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the steps of:
identifying a disabled processor node in the computing system, wherein the disabled processor node is installed, functional, and unutilized;
identifying one or more computing resources in the computing system that can be accessed only by the disabled processor node while the disabled processor node is enabled in the computing system; and
enabling one or more components of the disabled processor node required to access the one or more computing resources by enabling certain components including a memory controller of the disabled processor node without fully enabling the entire disabled processor node and without notifying an operating system of the computing system that any component of the disabled processor node in the computing system is enabled; and
wherein enabling the one or more components of the disabled processor node that is required to access the one or more computing resources includes preventing an entry for the disabled processor node from being added to a data structure that identifies all active devices in the computing system.

7. The apparatus of claim 6 further comprising computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the step of presenting, to the operating system of the computing system, the one or more computing resources that can be accessed only by the disabled processor node.

8. The apparatus of claim 6 further comprising computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the steps of:
receiving a request for capacity-on-demand, the request for capacity-on-demand requesting additional computing resources in the computing system; and
in response to receiving the request for capacity-on-demand, enabling the one or more components of the disabled processor node required to access the additional computing resources.

9. The apparatus of claim 6 wherein the one or more computing resources that can be accessed only by the disabled processor node in the computing system include one of more dual in-line memory modules (‘DIMMs’).

10. A computer program product comprising:
one or more computer-readable storage media and computer program instructions stored on the one or more computer-readable storage media, wherein the one or more computer-readable storage media is not a signal, the computer program instructions comprising:
computer program instructions to identify a disabled processor node in a computing system, wherein the disabled processor node is installed, functional, and unutilized;
computer program instructions to identify one or more computing resources in the computing system that can be accessed only by the disabled processor node while the disabled processor node is enabled in the computing system; and
computer program instructions to enable one or more components of the disabled processor node required to access the one or more computing resources by enabling certain components including a memory controller of the disabled processor node without fully enabling the entire disabled processor node and without notifying an operating system of the computing system that any component of the disabled processor node in the computing system is enabled; and
wherein enabling the one or more components of the disabled processor node that is required to access the one or more computing resources includes preventing an entry for the disabled processor node from being added to a data structure that identifies all active devices in the computing system.

11. The computer program product of claim 10 further comprising computer program instructions to present, to the operating system of the computing system, the one or more computing resources that can be accessed only by the disabled processor node.

12. The computer program product of claim 10 further comprising computer program instructions:
to receive a request for capacity-on-demand, requesting additional computing resources in the computing system; and
in response to receiving the request for capacity-on-demand, to enable the one or more components of the disabled processor node required to access the additional computing resources.

13. The computer program product of claim 10 wherein the one or more computing resources that can be accessed only by the disabled processor node in the computing system include one of more dual in-line memory modules (‘DIMMs’).

Assignees

• Lenovo Entpr Solutions Singapore Pte Ltd

Inventors

• Oliver Douglas W

Classifications

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title

• G06F2212/1028

  Power efficiency · CPC title

• G06F2212/1041

  Resource optimization · CPC title

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• G06F1/24

  Resetting means · CPC title