Flag non-modification extension for ISA instructions using prefixes

Patent metadata

Field	Value
Publication number	US-9811338-B2
Application number	US-201113976261-A
Country	US
Kind code	B2
Filing date	Nov 4, 2011
Priority date	Nov 14, 2011
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

In one embodiment, a processor includes an instruction decoder to receive and decode an instruction having a prefix and an opcode, an execution unit to execute the instruction based on the opcode, and flag modification override logic to prevent the execution unit from modifying a flag register of the processor based on the prefix of the instruction.

First claim

What is claimed is:

1. A method, comprising:
in response to decoding an instruction having a prefix and an opcode received at a processor, wherein the prefix includes a vector length bit when the opcode includes a vector instruction that is supported by the processor,
executing, by an execution unit of the processor, the instruction based on the opcode; and
preventing the execution unit from modifying a flag register of the processor based on the vector length bit of the prefix of the instruction.

2. The method of claim 1 , further comprising:
extracting the prefix from the instruction; and
determining whether the instruction is valid based on the prefix in view of a capability of the processor, wherein the execution unit is to execute the instruction only if the instruction is valid.

3. The method of claim 2 , wherein determining whether the instruction is valid comprises examining a value of one or more bits of the prefix in view of a processor identifier that identifies a type of the processor.

4. The method of claim 2 , further comprising generating an exception indicating that the instruction is invalid, if one or more bits of the prefix matches a predetermined bit pattern based on the capability of the processor.

5. The method of claim 1 , further comprising:
preventing the execution unit from modifying the flag register if one or more bits of the prefix match a first predetermined bit pattern; and
allowing the execution unit to modify the flag register if one or more bits of the prefix match a second predetermined bit pattern.

6. The method of claim 1 , wherein the opcode of the instruction represents an integer operation that when executed would normally modify the flag register.

7. A processor, comprising:
an instruction decoder to receive and decode an instruction having a prefix and an opcode, wherein the prefix includes a vector length bit when the opcode includes a vector instruction that is supported by the processor;
an execution unit to execute the decoded instruction based on the opcode; and
flag modification override logic to prevent the execution unit from modifying a flag register of the processor based on the vector length bit of the prefix of the instruction.

8. The processor of claim 7 , wherein the instruction decoder is to extract the prefix from the instruction and to determine whether the instruction is valid based on the prefix in view of a capability of the processor, wherein the execution unit is to execute the instruction only if the instruction is valid.

9. The processor of claim 8 , wherein the instruction decoder is to examine a value of one or more bits of the prefix in view of a processor identifier that identifies a type of the processor.

10. The processor of claim 8 , wherein the instruction decoder is to generate an exception indicating that the instruction is invalid, if one or more bits of the prefix matches a predetermined bit pattern based on the capability of the processor.

11. The processor of claim 7 , wherein the flag modification override logic is to
prevent the execution unit from modifying the flag register if one or more bits of the prefix match a first predetermined bit pattern, and
allow the execution unit to modify the flag register if one or more bits of the prefix match a second predetermined bit pattern.

12. The processor of claim 7 , wherein the opcode of the instruction represents an integer operation that when executed would normally modify the flag register.

13. A system, comprising:
an interconnect;
a processor coupled to the interconnect to:
receive and decode, by an instruction decoder of the processor, an instruction having a prefix and an opcode, wherein the prefix includes a vector length bit when the opcode includes a vector instruction that is supported by the processor,
execute the decoded instruction based on the opcode, and
prevent modification of a flag register of the processor based on the vector length bit of the prefix of the instruction; and

a dynamic random access memory (DRAM) coupled to the interconnect.

14. The system of claim 13 , wherein the processor is to extract the prefix from the instruction and to determine whether the instruction is valid based on the prefix in view of a capability of the processor, wherein the processor is to execute the instruction only if the instruction is valid.

15. The system of claim 14 , wherein the processor is to examine a value of one or more bits of the prefix in view of a processor identifier that identifies a type of the processor.

16. The system of claim 14 , wherein the processor is to generate an exception indicating that the instruction is invalid, if one or more bits of the prefix matches a predetermined bit pattern based on the capability of the processor.

17. The system of claim 13 , wherein the processor is to
prevent the execution unit from modifying the flag register if one or more bits of the prefix match a first predetermined bit pattern, and
allow the execution unit to modify the flag register if one or more bits of the prefix match a second predetermined bit pattern.

18. The system of claim 13 , wherein the opcode of the instruction represents an integer operation that when executed would normally modify the flag register.

Assignees

• Combs Jonathan D
• Brandt Jason W
• Valentine Robert
• Intel Corp

Inventors

• Combs Jonathan D
• Brandt Jason W
• Valentine Robert

Classifications

• G06F9/30094

  Condition code generation, e.g. Carry, Zero flag · CPC title

• G06F9/30145 Primary

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/30185

  according to one or more bits in the instruction, e.g. prefix, sub-opcode · CPC title