Low-power type-C receiver with high idle noise and DC-level rejection

Patent metadata

Field	Value
Publication number	US-9811135-B2
Application number	US-201514977589-A
Country	US
Kind code	B2
Filing date	Dec 21, 2015
Priority date	Jun 19, 2015
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

Techniques for low-power USB Type-C receivers with high DC-level shift tolerance and high noise rejection are described herein. In an example embodiment, a USB-enabled device comprises a receiver circuit coupled to a Configuration Channel (CC) line of a USB Type-C subsystem. The receiver circuit is configured to receive data from an incoming signal on the CC line even when the incoming signal has more than 250 mV of DC offset with respect to local ground, and to reject the incoming signal even when the incoming signal includes noise with a magnitude of more than 300 mVpp.

First claim

What is claimed is:

1. A device comprising a receiver circuit coupled to a Configuration Channel (CC) line of a Universal Serial Bus (USB) Type-C subsystem, wherein the receiver circuit is configured to receive valid BMC-encoded data from an incoming signal on the CC line when the incoming signal has more than 250 mV of direct current (DC) offset with respect to local ground.

2. The device of claim 1 , wherein the receiver circuit is further configured to reject the incoming signal when the incoming signal comprises noise with a magnitude of more than 300 mVpp.

3. The device of claim 2 , wherein the magnitude of the noise is in one of: a first range from 300 mVpp to 350 mVpp; a second range from 350 mVpp to 400 mVpp; a third range from 400 mVpp to 450 mVpp; or a fourth range from 450 mVpp to 500 Vpp.

4. The device of claim 2 , wherein the incoming signal comprises the noise during idle condition.

5. The device of claim 1 , wherein the receiver circuit comprises:
a capacitor coupled in series from the CC line to a restore node, the capacitor configured to block a DC component of the incoming signal on the CC line;
a restoration circuit coupled to the restore node and configured to shift a voltage of the incoming signal to a first reference voltage; and
a slicer circuit coupled to the restore node and configured to compare the shifted voltage to a second reference voltage.

6. The device of claim 5 , wherein the restoration circuit comprises:
a first comparator configured as an operational amplifier in a feedback loop;
a current source controlled by an output of the first comparator; and
a current sink coupled to the restore node;
wherein the restore node couples the capacitor to an output of the current source and to an input of the first comparator.

7. The device of claim 6 , wherein the slicer circuit comprises a second comparator, and wherein a first input of the second comparator is coupled to the restore node and a second input of the second comparator is coupled to the second reference voltage.

8. The device of claim 5 , wherein the first reference voltage and the second reference voltage are configured to define a voltage threshold at which an output of the slicer circuit is toggled to indicate that the incoming signal is not noise.

9. The device of claim 8 , wherein the voltage threshold is up to 500 mVpp.

10. The device of claim 8 , wherein the device is configured to remain in a sleep state when the shifted voltage is at or below the voltage threshold.

11. The device of claim 1 , wherein the device comprises an integrated circuit (IC) chip, wherein the IC chip includes the USB Type-C subsystem and the USB Type-C subsystem includes the receiver circuit.

12. The device of claim 1 , wherein the device is a cable.

13. An integrated circuit (IC) controller comprising:
a Universal Serial Bus (USB) Type-C subsystem; and
a receiver circuit coupled to a Configuration Channel (CC) line of the USB Type-C subsystem, the receiver circuit comprising:
a capacitor coupled in series from the CC line to a restore node, the capacitor configured to block a direct current (DC) component of an incoming signal on the CC line;
a restoration circuit coupled to the restore node and configured to shift a voltage of the incoming signal to a first reference voltage; and
a slicer circuit coupled to the restore node and configured to compare the shifted voltage to a second reference voltage.

14. The IC controller of claim 13 , wherein the restoration circuit comprises:
a first comparator configured as an operational amplifier in a feedback loop;
a current source controlled by an output of the first comparator; and
a current sink coupled to the restore node;
wherein the restore node couples the capacitor to an output of the current source and to an input of the first comparator.

15. The IC controller of claim 14 , wherein the slicer circuit comprises a second comparator, and wherein a first input of the second comparator is coupled to the restore node and a second input of the second comparator is coupled to the second reference voltage.

16. The IC controller of claim 13 , wherein the first reference voltage and the second reference voltage are configured to define a voltage threshold of up to 500 mVpp, and wherein an output of the slicer circuit is toggled to indicate that the incoming signal is not noise when the shifted voltage is above the voltage threshold.

17. The IC controller of claim 13 , wherein the receiver circuit is configured to receive data from the incoming signal on the CC line when the incoming signal has more than 250 mV of DC offset with respect to local ground.

18. A system comprising:
a Universal Serial Bus (USB) Type-C cable; and
a USB-enabled device attached to the USB Type-C cable, the USB-enabled device comprising a receiver circuit coupled to a Configuration Channel (CC) line of the USB Type-C cable, wherein the receiver circuit is configured to receive valid BMC-encoded data from an incoming signal on the CC line when the incoming signal has more than 250 mV of direct current (DC) offset with respect to local ground.

19. The system of claim 18 , wherein the receiver circuit is further configured to reject the incoming signal when the incoming signal comprises noise with a magnitude of more than 300 mVpp.

20. The system of claim 19 , wherein the magnitude of the noise is in a range from 300 mVpp to 500 mVpp.

Assignees

• Cypress Semiconductor Corp

Inventors

• Agarwal Rishi
• Bodnaruk Nicholas Alexander

Classifications

• G06F13/385

  for adaptation of a particular data processing system to different peripheral devices · CPC title

• G06F1/266 Primary

  Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• H02J7/00

  Circuit arrangements for charging or discharging batteries or for supplying loads from batteries · CPC title

• G06F1/22 Primary

  Means for limiting or controlling the pin/gate ratio · CPC title