Core testing machine

Patent metadata

Field	Value
Publication number	US-9810735-B2
Application number	US-201514866720-A
Country	US
Kind code	B2
Filing date	Sep 25, 2015
Priority date	Sep 25, 2015
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

A core testing executor/processor for testing a plurality of devices simultaneously using virtualization containers to connect to interfaces of corresponding devices under test is disclosed.

First claim

We claim:

1. A system for testing devices, the system comprising:
a testing machine with a plurality of slots, wherein each slot of the plurality of slots is for installing a device-under-test (DUT) of a plurality of DUTs;
a plurality of core testing processors, wherein each core testing processor of the plurality of core testing processors communicates with a user interface and is associated with a respective slot of the plurality of slots, and wherein each core testing processor of at least a subset of the plurality of core testing processors is associated with a respective web socket for communication that is isolated and independent of communication associated with other core testing processors of the plurality of core testing processors; and
a plurality of lightweight virtualization containers, where a respective lightweight virtualization container of the plurality of lightweight virtualization containers is associated with an interface of a DUT that is installed for testing, wherein the plurality of lightweight virtualization containers enable isolation of respective testing processes and testing resources associated with each respective DUT;
wherein a respective core testing processor of the plurality of core testing processors retrieves at run time a respective test configuration corresponding to the DUT installed in the respective slot associated with a respective core testing processor,
loads the set of tests associated with the DUT installed in the respective slot associated with respective core testing processor, and
executes the loaded set of tests.

2. The system of claim 1 , wherein the plurality of lightweight virtualization containers comprise testing probes for testing corresponding interfaces of a respective DUT of the plurality of DUTs.

3. The system of claim 1 ; wherein the plurality of lightweight virtualization containers are used for testing one or more DUT interfaces at the DUT, each of the interfaces comprising at least one of:
an Ethernet Local Area Network (LAN) interface; an Ethernet Wide Area Network (WAN) interface; a Multimedia over Coax Affiance (MoCA) LAN interface; a Multimedia over Coax Alliance (MoCA) WAN interface; a Wireless 2.4 GHz interface; a Wireless 5.0 GHz interface; a Foreign exchange Subscriber ports (FXS) interface; a Universal Serial Bus (USB) interface; a video interface; and an audio interface.

4. The system of claim 1 , wherein the respective core testing processor of the plurality of core testing processors communicates using asynchronous feedback and interaction.

5. The system of claim 1 , wherein the respective core testing processor of the plurality of core testing processors communicates using Java script object notation (JSON) messages.

6. The system of claim 1 , wherein the respective core testing processor of the plurality of core testing processors communicates using TCP/IP protocol.

7. A method for testing devices, comprising the steps of: scanning identification information associated with each device under test (DUT) of a plurality of devices under test;
validating each DUT by receiving, at a core executor, serial number information for each DUT;
retrieving, at the core executor, from a source selected from a database and a web service, type information comprising a make and/or model of each DUT, retrieval of the type information based upon the serial number information; loading, at the core executor, test configuration information specific to each type of DUT; reading a test step of the test configuration information loaded for each DUT; executing the test step read for each DUT;
determining whether each DUT passed or faded the executed test step; responsive to a determination that a DUT passed the executed test step, determining whether, for each DUT that passed the executed test step, the loaded test configuration information contains a next test step to be executed; responsive to a determination that the loaded test configuration contains a next test step to be executed, repeating, for each DUT for which a next test step exists, the steps of reading the test step, executing the test step read for each DUT, determining whether each DUT passed the executed test step, and determining whether, for each DUT that passed the executed test step, the loaded test configuration information contains a next step to be executed; and responsive to a determination that the loaded test configuration does not contain a next test step to be executed, terminating the repeating step for each DUT for which a next test step does not exist.

8. The method of claim 7 , further comprising the steps of: responsive to a determination that a DUT faded the executed test step, determining whether to abort testing for each DUT that failed the executed test step; and responsive to a determination to not abort testing, executing the repeating step until reaching the determination that the loaded test configuration does not contain a next test step to be executed.

9. The method claim 8 , further comprising the step of, responsive to a determination to abort testing, indicating testing failure for each DUT for which a determination to abort testing has been made.

10. The method of claim 8 , further comprising the step of communicating, upon completion of each test step, results of the completed test step to a user.

11. The method of claim 10 , wherein the step of communicating comprises sending a message to a browser of the user via web-sockets.

Assignees

• Contec Llc

Inventors

• Kumar Samant
• Kumar Dinesh
• Diddimani Shivashankar
• Samaiya Gunjan

Classifications

• G06F11/273 Primary

  Tester hardware, i.e. output processing circuits {(G06F11/263 takes precedence)} · CPC title

• G01R31/3177

  Testing of logic operation, e.g. by logic analysers · CPC title

• G01R31/31715 Primary

  Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer · CPC title