Burst mode clock data recovery device and method thereof

Patent metadata

Field	Value
Publication number	US-9806879-B2
Application number	US-201615159146-A
Country	US
Kind code	B2
Filing date	May 19, 2016
Priority date	May 28, 2015
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

A burst mode clock data recovery device includes a clock data recovery loop, a frequency tracking loop, a frequency tracking loop, and a fast-locking unit. The clock data recovery loop receives a sampling clock signal and a data signal and uses the sampling clock signal to lock the data signal to generate a recovery clock signal. The frequency tracking loop tracks a frequency of the recovery clock signal to generate a frequency detection signal associated with the recovery clock signal. The phase lock loop receives the frequency detection signal and locks the recovery clock signal in a reference clock. The fast-locking unit generates a fast-locking signal according to the recovery clock signal and a first phase detection signal to allow the clock data recovery loop to quickly lock the data signal after the transition from a stall mode to the burst mode.

First claim

What is claimed is:

1. A clock data recovery device, comprising:
a clock data recovery loop for receiving a sampling clock signal and a data signal and using the sampling clock signal to lock the data signal to generate a recovery clock signal;
a frequency tracking loop coupled to the clock data recovery loop for tracking a frequency of the recovery clock signal to generate a frequency detection signal associated with the recovery clock signal;
a phase lock loop coupled to the clock data recovery loop and the frequency tracking loop for receiving the frequency detection signal and locking the recovery clock signal in a reference clock; and
a fast-locking unit coupled to the clock data recovery loop for generating a fast-locking signal under a burst mode according to the recovery clock signal and a first phase detection signal to allow the clock data recovery loop to lock the data signal after the transition from a stall mode to the burst mode.

2. The device as claimed in claim 1 , wherein the clock data recovery loop comprises:
a first phase detector for detecting a phase difference between the sampling clock signal and the data signal to generate the first phase detection signal;
a first charge pump for generating a voltage control signal according to the first phase detection signal;
a voltage-controlled oscillator for generating the recovery clock signal according to the voltage control signal; and
a first low-pass filter for performing a low-pass filtering operation on the voltage control signal.

3. The device as claimed in claim 2 , wherein the fast-locking unit is a phase interpolator, the phase interpolator performs interpolation on the recovery clock signal to generate the sampling clock signal and relies on the first phase detection signal of the first phase detector to recognize phase-leading or phase-lag of a sampling position of the data signal to adjust a phase of the sampling clock signal , so that the sampling clock signal is allowed to be aligned with a temporal position of the data signal.

4. The device as claimed in claim 3 , wherein the fast-locking unit scans multiple phases of multiple sampling clock signals and finds out a phase of the multiple phases substantially aligned with the temporal position of the data signal.

5. The device as claimed in claim 2 , wherein the fast-locking unit is an oversampling device, the oversampling device uses multiple phases of multiple recovery clock signals generated by the voltage-controlled oscillator to fetch the data signal and obtain multiple edge positions and middle positions of data of the data signal, selects a phase of the multiple phases according to the multiple edge positions and middle positions of data, and select a voltage control signal corresponding to the selected phase to generate the recovery clock signal.

6. The device as claimed in claim 2 , wherein the phase lock loop comprises:
a second phase detector for receiving the reference clock and a frequency division signal and generating a second phase detection signal according to a phase difference between the reference clock and the frequency division signal;
a second charge pump for generating a voltage control signal according to the second phase detection signal; and
a fractional-N frequency divider for receiving the recovery clock signal and the frequency detection signal and generating the frequency division signal according to the recovery clock signal and the frequency detection signal.

7. The device as claimed in claim 6 , wherein the frequency tracking loop comprises:
a frequency detector for receiving the reference clock and detecting a frequency of the recovery clock signal relying on the reference clock to generate the frequency detection signal.

8. The device as claimed in claim 6 , wherein the frequency tracking loop further comprising:
a second low-pass filter for performing a low-pass filtering operation on the frequency detection signal.

Assignees

• Realtek Semiconductor Corp

Inventors

• Gu Lijun
• Li Ming
• Chen Ling

Classifications

• H04L7/033

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title

• H04L7/0087 Primary

  Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection · CPC title

• H04L7/0025

  interpolation of clock signal · CPC title

• H03L7/10

  for assuring initial synchronisation or for broadening the capture range · CPC title

• H04L7/0004

  Initialisation of the receiver (H04L7/0075 and H04L7/10 take precedence) · CPC title