Amplifier circuit

Patent metadata

Field	Value
Publication number	US-9806728-B1
Application number	US-201715441075-A
Country	US
Kind code	B1
Filing date	Feb 23, 2017
Priority date	Sep 1, 2016
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

An amplifier circuit includes a sampling circuit and an amplifier connected to an output of the sampling circuit. A feedback capacitor is between an output terminal of the amplifier and an output terminal of the sampling circuit. A quantizer that includes a comparator is configured to quantize a voltage at the output terminal of the sampling circuit according to a comparison of a voltage at the output terminal of the sampling circuit to a voltage at the reference potential terminal of the comparator. The quantizer outputs a digital code according to the voltage comparison. A control circuit receives the digital code from the quantizer and stores the digital code in a register as a cancellation digital code. A digital-analog (D/A) converter outputs an analog signal in accordance with digital codes from the control circuit.

First claim

What is claimed is:

1. An amplifier circuit, comprising:
a sampling circuit configured to sample a voltage of an input signal;
an amplifier having an input terminal connected to an output terminal of the sampling circuit;
a feedback capacitor connected between an output terminal of the amplifier and the output terminal of the sampling circuit;
a quantizer including a comparator that has a first input terminal connected to the output terminal of the sampling circuit and a second input terminal connected to a reference potential terminal, the quantizer configured to quantize a voltage at the output terminal of the sampling circuit according to a comparison of the voltage at the output terminal of the sampling circuit to a voltage at the reference potential terminal and to output a digital code according to the comparison;
a control circuit receiving the digital code from the quantizer and including a register for storing the digital code as a cancellation digital code for cancelling a difference between an offset of the amplifier and an offset of the comparator; and
a first digital-analog (D/A) converter configured to output an analog signal in accordance with digital codes from the control circuit.

2. The amplifier circuit according to claim 1 , wherein
the sampling circuit outputs an offset voltage for acquiring the cancellation digital code before the quantizer processes the input signal,
the quantizer quantizes the output offset voltage and outputs the cancellation digital code, and
the control circuit stores the cancellation digital code output from the quantizer in the register.

3. The amplifier circuit according to claim 1 , wherein
the control circuit outputs the cancellation digital code stored in the register to the first D/A converter when a timing signal is received, and
the first D/A converter outputs the analog signal according to the cancellation digital code output from the control circuit while the input signal is being processed.

4. The amplifier circuit according to claim 1 , wherein
the control circuit outputs the cancellation digital code stored in the register to the quantizer when a timing signal is received,
the quantizer can be operated at a plurality of quantization levels and a quantization level at which the quantizer operates to process the input signal can be altered according to the cancellation digital code.

5. The amplifier circuit according to claim 1 , further comprising:
a second digital-analog (D/A) converter configured to generate an analog signal in accordance with the cancellation digital code, wherein
the analog signal generated by the second D/A converter is applied to the first input terminal of the comparator while the input signal is being processed.

6. The amplifier circuit according to claim 1 , wherein the quantizer is a flash analog-to-digital converter (ADC).

7. The amplifier circuit according to claim 1 , wherein the first D/A converter includes:
an output terminal that carries the analog signal output from the first D/A converter;
a plurality of buffers in which one buffer for each bit of the digital code is provided; and
a plurality of capacitors, each capacitor in the plurality of capacitors coupling one buffer in the plurality of buffers to the output terminal of the first D/A converter, wherein
a capacitance value for a capacitor in the plurality of capacitors that corresponds to a more significant bit in the digital code is twice a capacitance value of a capacitor in the plurality of capacitors that corresponds to a less significant bit that is adjacent to the more significant bit in the digital code.

8. The amplifier circuit according to claim 1 , further comprising a coupling capacitor, wherein
the first D/A converter is a R-2R resistor DAC having an analog output that is coupled to an output terminal of the first D/A converter by the coupling capacitor.

9. The amplifier circuit according to claim 1 , wherein
the comparator is configured to perform a plurality of comparisons of the voltage at the output terminal of the sampling circuit to the voltage at the reference potential terminal of the comparator, and
the voltage at the output terminal of the sampling circuit is altered after each comparison of the comparator.

10. The amplifier circuit according to claim 1 , wherein the sampling circuit includes:
a first switch, a second switch, and a third switch; and
a sampling capacitor, a first terminal of the sampling capacitor being connected to the input signal when the first switch is closed and to a reference potential when the second switch is closed, and a second terminal of the sampling capacitor being connected to the reference potential when the third switch is closed.

11. An amplifier circuit, comprising:
a sampling circuit configured to sample a voltage of an input signal;
an amplifier having an input terminal connected to an output terminal of the sampling circuit;
a feedback capacitor connected between an output terminal of the amplifier and the output terminal of the sampling circuit;
a quantizer including a comparator that has an input terminal connected to the output terminal of the sampling circuit and configured to quantize voltage at the output terminal of the sampling circuit using a comparison result from the comparator and to output a digital code according to the comparison; and
a control circuit including:
an input terminal connected to the output terminal of the sampling circuit, and
a register for storing a cancellation digital code for cancelling the difference between an offset of the amplifier and an offset of the comparator in response to a code storing signal;
an offset control circuit that outputs the cancellation digital code stored in the register in response to an active calibration signal; and
a signal control circuit that outputs the digital code from the quantizer in response to an inactive calibration signal; and

a first digital-analog (D/A) converter configured to output an analog signal in accordance with digital codes from the control circuit.

12. The amplifier circuit according to claim 11 further comprising:
a controller coupled to the sampling circuit and configured to provide the active and inactive calibration signals.

13. The amplifier circuit according to claim 12 , wherein
the controller is further configured to provide a code storing signal, and
the control circuit couples the amplifier output to the output of the first D/A converter in response to an active code storing signal.

14. The amplifier circuit according to claim 11 , further comprising:
a second D/A converter configured to generate an analog signal in accordance with the cancellation digital code, wherein
the analog signal generated by the second D/A converter is applied to the input terminal of the comparator while the input signal is being processed.

15. The amplifier circuit according to claim 11 , wherein the quantizer is a flash analog-to-digital converter (ADC).

16. The amplifier circuit according to claim 11 , wherein the first D/A converter includes:
an output terminal that carries the analog signal output from the first D/A converter;
a plurality of buffers in which one buffer for each bit of the digital code is provided; and
a plurality of capacitors, each capacitor in the plurality of capacitors coupling one buffer in the plurality of buffers to the output terminal of the first D/A converter, wherein
a capacitance value for a capacitor in the plurality of capacitors that corresponds to a more significant bit in the digital code is twice a capacitance value

Assignees

• Toshiba Kk

Inventors

• Sugimoto Tomohiko
• Ishii Hirotomo
• Yoshioka Kentaro

Classifications

• H03M1/0602

  of deviations from the desired transfer characteristic (H03M1/0617 takes precedence) · CPC title

• H03M1/46

  with digital/analogue converter for supplying reference values to converter · CPC title

• H03F3/45596

  by offset reduction · CPC title

• H03M1/0607

  Offset or drift compensation (removal of offset already present on the analogue input signal H03M1/1295) · CPC title

• H03M1/001 Primary

  Analogue/digital/analogue conversion · CPC title