System and method for signal amplification using a resistance network

Patent metadata

Field	Value
Publication number	US-9806687-B2
Application number	US-201615078199-A
Country	US
Kind code	B2
Filing date	Mar 23, 2016
Priority date	Mar 23, 2016
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

A signal amplification method includes receiving, from a capacitive sensor, a first input signal by a first control terminal of a first transistor, and a second input signal by a first control terminal of a second transistor. The method also includes producing a first output signal, including amplifying a first signal at a first load path terminal of the first transistor using a first inverting amplifier having an output coupled to a resistance network, and producing a second output signal, including amplifying a second signal at a first load path terminal of the second transistor using a second inverting amplifier having an output coupled to the resistance network. The method also includes feeding back the first and second output signal to a second load path terminal of the first transistor and to a second load path terminal of the second transistor via the resistance network according to a pre-determined fraction.

First claim

What is claimed is:

1. An amplification device, comprising:
a resistance network coupled between a first output of the amplification device and a second output of the amplification device,
a first transistor having a control terminal coupled to a first input node of the amplification device and a first load path terminal coupled to the resistance network at a first node;
a second transistor having a control terminal coupled to a second input node of the amplification device and a first load path terminal coupled to the resistance network at a second node, wherein at least one of the first input node and the second input node is configured to be coupled to a capacitive sensor;
a first inverting amplifier comprising an input coupled to a second load path terminal of the first transistor and an output coupled to a first output node of the amplification device, wherein the first inverting amplifier comprises
a third current source,
a third transistor having a first load path terminal coupled to the second load path terminal of the first transistor,
a second load path terminal coupled to the third current source, and
a fourth transistor having a first load path terminal coupled to the first output node, and a control terminal coupled to the second load path terminal of the third transistor; and

a second inverting amplifier comprising an input coupled to a second load path terminal of the second transistor and an output coupled to a second output node of the amplification device, wherein the second inverting amplifier comprises
a fourth current source,
a fifth transistor having a first load path terminal coupled to the second load path terminal of the second transistor, and a second load path terminal coupled to the fourth current source, and
a sixth transistor having a first load path terminal coupled to the second output node, and a control terminal coupled to the second load path terminal of the fifth transistor.

2. The amplification device of claim 1 , further comprising:
at least one of a first current source or a first degeneration resistor, coupled to the second load path terminal of the first transistor and to a first reference voltage; and
at least one of a second current source or a second degeneration resistor, coupled to the second load path terminal of the second transistor and to the first reference voltage.

3. The amplification device of claim 2 , wherein:
each of the first transistor, the second transistor, the fourth transistor, the sixth transistor, the third current source, and the fourth current source comprises a metal oxide semiconductor field effect transistor (MOSFET) having a first channel type,
each of the third transistor, the fifth transistor, the first current source, and the second current source comprises a MOSFET having a second channel type; and
each of the first channel type and the second channel type comprise opposite channel types selected from a p-channel type or an n-channel type.

4. The amplification device of claim 2 , further comprising:
a first bias resistor coupled between the first input node and a reference voltage; and
a second bias resistor coupled between the second input node and a second reference voltage.

5. The amplification device of claim 2 , wherein:
the first load path terminal of the first transistor is coupled to the first output node of the amplification device; and
the first load path terminal of the second transistor is coupled to the second output node of the amplification device.

6. The amplification device of claim 2 , wherein:
a second control terminal of the first transistor is coupled to one of a second reference voltage or a third node of the resistance network; and
a second control terminal of the second transistor is coupled to one of the second reference voltage or a fourth node of the resistance network.

7. An amplification device, comprising:
a resistance network coupled between a first output of the amplification device and a second output of the amplification device,
a first transistor having a control terminal coupled to a first input node of the amplification device and a first load path terminal coupled to the resistance network at a first node;
a second transistor having a control terminal coupled to a second input node of the amplification device and a first load path terminal coupled to the resistance network at a second node, wherein at least one of the first input node and the second input node is configured to be coupled to a capacitive sensor;
a first inverting amplifier comprising an input coupled to a second load path terminal of the first transistor and an output coupled to a first output node of the amplification device; and
a second inverting amplifier comprising an input coupled to a second load path terminal of the second transistor and an output coupled to a second output node of the amplification device;
a first resistance coupled between a second control terminal of the first transistor and a third node of the resistance network;
a second resistance coupled between the second control terminal of the first transistor and the output of the first inverting amplifier;
a third resistance coupled between a second control terminal of the second transistor and the third node of the resistance network; and
a fourth resistance coupled between the second control terminal of the second transistor and the output of the second inverting amplifier; and wherein:
a voltage gain of the amplification device is in accordance with a ratio of the second resistance divided by the first resistance, and
a ratio of the fourth resistance divided by the third resistance is the same as the ratio of the second resistance divided by the first resistance.

8. The amplification device of claim 7 , wherein:
the first load path terminal of the first transistor is directly connected to the output of the first inverting amplifier; and
the first load path terminal of the second transistor is directly connected to the output of the second inverting amplifier.

9. The amplification device of claim 7 , further comprising:
a first switch network coupled to the resistance network; and
a second switch network coupled to the resistance network, wherein
the first resistance and the second resistance are each selectable by configuring the first switch network in accordance with a voltage gain setting, and
the third resistance and the fourth resistance are each selectable by configuring the second switch network in accordance with the voltage gain setting.

10. The amplification device of claim 7 , wherein:
the first load path terminal of the first transistor is coupled to the second control terminal of the first transistor;
the first load path terminal of the second transistor is coupled to the second control terminal of the second transistor;
the second control terminal of the first transistor is a body terminal; and
the second control terminal of the second transistor is a body terminal.

11. A method for signal amplification, comprising:
receiving, by a first control terminal of a first transistor, a first input signal from a capacitive sensor;
receiving, by a first control terminal of a second transistor, a second input signal from the capacitive sensor;
producing a first output signal, producing the first output signal comprising amplifying a first signal at a first load path terminal of the first transistor using a first inverting amplifier having an output coupled to a resistance network, and receiving, at a load path terminal of a third transistor comprised in the first inverting amplifier, the first signal from the first load path terminal of the first transistor;
producing a

Assignees

• Infineon Technologies Ag

Inventors

• Valli Luca
• Muehlbacher Benno
• Gaggl Richard

Classifications

• H03F3/45179

  using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title

• H03G1/0088 Primary

  using discontinuously variable devices, e.g. switch-operated · CPC title

• H03F2203/45222

  the differential amplifier output being directly controlled by a feedback or feedforward circuit coupled at the output of the dif amp · CPC title

• H03F2203/45138

  Two or more differential amplifiers in IC-block form are combined, e.g. measuring amplifiers · CPC title

• H03F2203/45512

  the FBC comprising one or more capacitors, not being switched capacitors, and being coupled between the LC and the IC · CPC title