Thin film transistor substrate, display device including a thin film transistor substrate, and method of forming a thin film transistor substrate

US9806105B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9806105-B2
Application numberUS-201615295128-A
CountryUS
Kind codeB2
Filing dateOct 17, 2016
Priority dateOct 27, 2015
Publication dateOct 31, 2017
Grant dateOct 31, 2017

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  5. First independent claim

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Abstract

Official abstract text for this publication.

Provided are a thin film transistor (TFT) substrate, a display device, and a method of forming the TFT. A TFT substrate includes: a first TFT including: a polycrystalline semiconductor (PS) layer, a first gate electrode (GE) overlapping the PS layer, a nitride layer (NL) on the first GE, an oxide layer (OL) on the NL, and a first source electrode and a first drain electrode on the OL, and a second TFT including: a second GE on a same layer as the first GE, a hydrogen collecting layer between the second GE and the NL, an oxide semiconductor (OS) layer on the OL, a second source electrode and a second drain electrode contacting respective sides of the OS layer, wherein the first TFT and the second TFT are disposed on a same substrate, and wherein the NL includes an opening exposing the hydrogen collecting layer of the second TFT.

First claim

Opening claim text (preview).

What is claimed is: 1. A thin film transistor substrate, comprising: a first thin film transistor comprising: a polycrystalline semiconductor layer; a first gate electrode overlapping the polycrystalline semiconductor layer; a nitride layer on the first gate electrode; an oxide layer on the nitride layer; and a first source electrode and a first drain electrode on the oxide layer; and a second thin film transistor comprising: a second gate electrode on a same layer as the first gate electrode; a hydrogen collecting layer between the second gate electrode and the nitride layer; an oxide semiconductor layer on the oxide layer; a second source electrode contacting one side of the oxide semiconductor layer; and a second drain electrode contacting the other side of the oxide semiconductor layer, wherein the first thin film transistor and the second thin film transistor are disposed on a same substrate, wherein the nitride layer comprises an opening exposing the hydrogen collecting layer of the second thin film transistor, and wherein the opening of the nitride layer overlaps the oxide semiconductor layer in a vertical direction. 2. The thin film transistor substrate of claim 1 , wherein the oxide semiconductor layer overlaps the hydrogen collecting layer with only the oxide layer interposed between them. 3. The thin film transistor substrate of claim 1 , wherein the hydrogen collecting layer comprises a material comprising at least one of: indium gallium zinc oxide (IGZO), indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO). 4. The thin film transistor substrate of claim 1 , wherein the hydrogen collecting layer includes a material having a difference in an etch rate between a material of the second gate electrode and the material of the hydrogen collecting layer. 5. A flat panel display device, comprising: a display comprising the thin film transistor substrate of claim 1 . 6. The flat panel display device of claim 5 , wherein the display comprises one of: a liquid crystal display (LCD) device, a plasma display panel (PDP), an organic light-emitting diode (OLED) display device, and a electrophoresis display (ED) device. 7. The thin film transistor substrate of claim 1 , wherein the hydrogen collecting layer: is on the second gate electrode; and overlaps the second gate electrode in the vertical direction. 8. The thin film transistor substrate of claim 1 , wherein the opening of the nitride layer is on the second gate electrode, with the hydrogen collecting layer interposed therebetween. 9. A method of forming a thin film transistor substrate, the method comprising: providing a first thin film transistor comprising: providing a polycrystalline semiconductor layer; providing a first gate electrode overlapping the polycrystalline semiconductor layer; providing a nitride layer on the first gate electrode; providing an oxide layer on the nitride layer; and providing a first source electrode and a first drain electrode on the oxide layer; and providing a second thin film transistor comprising: providing a second gate electrode on a same layer as the first gate electrode; providing a hydrogen collecting layer between the second gate electrode and the nitride layer; providing an oxide semiconductor layer on the oxide layer; providing a second source electrode contacting one side of the oxide semiconductor layer; and providing a second drain electrode contacting the other side of the oxide semiconductor layer, wherein the first thin film transistor and the second thin film transistor are disposed on a same substrate, wherein the providing the nitride layer comprises forming an opening exposing the hydrogen collecting layer of the second thin film transistor, and wherein the opening of the nitride layer overlaps the oxide semiconductor layer in a vertical direction. 10. The method of claim 9 , wherein the oxide semiconductor layer overlaps the hydrogen collecting layer with only the oxide layer interposed between them. 11. The method of claim 9 , wherein the hydrogen collecting layer comprises a material comprising at least one of: indium gallium zinc oxide (IGZO), indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO). 12. The method of claim 9 , wherein the providing the hydrogen collecting layer includes providing a material having a difference in an etch rate between a material of the second gate electrode and the material of the hydrogen collecting layer.

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What does patent US9806105B2 cover?
Provided are a thin film transistor (TFT) substrate, a display device, and a method of forming the TFT. A TFT substrate includes: a first TFT including: a polycrystalline semiconductor (PS) layer, a first gate electrode (GE) overlapping the PS layer, a nitride layer (NL) on the first GE, an oxide layer (OL) on the NL, and a first source electrode and a first drain electrode on the OL, and a sec…
Who is the assignee on this patent?
Lg Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification H01L27/1251. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 31 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).