Semiconductor package

Patent metadata

Field	Value
Publication number	US-9806053-B2
Application number	US-201615185063-A
Country	US
Kind code	B2
Filing date	Jun 17, 2016
Priority date	Oct 11, 2013
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

A semiconductor package includes a first substrate, a first conductive layer, a first surface mount device (SMD) and a first bonding wire. The first substrate has a first top surface. The first conductive layer is formed on the first top surface and has a first conductive element and a second conductive element separated from each other. The first SMD is mounted on the first top surface, overlapping with but electrically isolated from the first conductive element. The first bonding wire electrically connects the first SMD with the first conductive layer.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a first substrate having a first top surface;
a first conductive layer formed on the first top surface and having a first conductive element and a second conductive element separated from each other;
a first surface mount device (SMD) mounted on the first top surface, overlapping with and electrically isolated from the first conductive element; and
a first bonding wire electrically connect the first SMD with the first conductive layer.

2. The semiconductor package according to claim 1 , further comprising:
a solder resistance layer covering a portion of the first conductive layer and allowing the first SMD mounted thereon;
a second SMD mounted on and directly contacted to the second conductive element; and
a second bonding wire electrically connecting the second SMD with the first conductive layer.

3. The semiconductor package according to claim 2 , wherein the first conductive layer further comprises:
a first bonding area of a third conductive element defined by the solder resistance layer on the first conductive layer and electrically connected to a power circuit through a first interconnection; and
a second bonding area of a fourth conductive element defined by the solder resistance layer on the first conductive layer and electrically connected to a ground circuit through a second interconnection.

4. The semiconductor package according to claim 3 , wherein the first SMD comprises:
a first electrode electrically connected to the first bonding area through the first bonding wire; and
a second electrode electrically connected to the second bonding area through a third bonding wire.

5. The semiconductor package according to claim 3 , wherein the second SMD comprises:
a first input/out (I/O) pad electrically connected to the first bonding area through the second bonding wire; and
a second I/O pad electrically connected to the second bonding area through a fourth bonding wire.

6. The semiconductor package according to claim 3 , wherein the first interconnection comprises:
a via-plug passing through the first substrate; and
a ball pad formed on a bottom surface of the first substrate opposite to the first top surface, electrically connected to the via-plug, and departed from the via-plug for a lateral distance substantially less than 5 mm.

7. The semiconductor package according to claim 1 , further comprising a second substrate mounted on the first top surface; wherein the first SMD is mounted on a second top surface of the second substrate departed from the first top surface.

8. The semiconductor package according to claim 7 , further comprising:
a second conductive layer formed of the second top surface;
a fifth bonding wire electrically connecting the first conductive layer with the second conductive layer; and
a sixth bonding wire electrically connecting the first SMD with the second conductive layer.

9. The semiconductor package according to claim 7 , further comprising a third SMD mounted on the second top surface and electrically connected to the first SMD.

10. A semiconductor package, comprising:
a first substrate having a first top surface;
a first conductive layer formed on the first top surface and having a first conductive element and a second conductive element separated from each other;
a first surface mount device (SMD) mounted on the first top surface, overlapping with and electrically isolated from the first conductive element;
a first bonding wire electrically connect the first SMD with the first conductive layer; and
a second SMD having a second top surface disposed between the first substrate and the first SMD, through which the first SMD is mounted on the second top surface and electrically isolated from the first conductive element.

11. The semiconductor package according to claim 10 , wherein the first SMD comprises:
a first electrode electrically connected to a first I/O pad of the second SMD through the first bonding wire; and
a second electrode electrically connected to a second I/O pad of the second SMD through a third bonding wire.

12. The semiconductor package according to claim 11 , wherein the first conductive layer comprises a power pad and a ground pad, and the first I/O pad is electrically connected to the power pad through a fourth bonding wire and further electrically connected to a power circuit through a first interconnection; and the second I/O pad is electrically connected to the ground pad through a fifth bonding wire and further electrically connected to a ground circuit through a second interconnection.

13. The semiconductor package according to claim 12 , wherein the second SMD further comprises a third I/O pad disposed adjacent to the first I/O pad and electrically connected to the first electrode by a sixth bonding wire.

14. The semiconductor package according to claim 13 , wherein the third I/O pad and the first I/O pad are arranged along a line substantially parallel to one side of the second SMD and have a level pitch substantially less than 500 μm.

15. The semiconductor package according to claim 12 , wherein the second SMD further comprises a third I/O pad, the third I/O pad and the first I/O pad are respectively arranged in two lines substantially parallel to one side of the second SMD and has a bevel pitch substantially less than 700 μm.

16. The semiconductor package according to claim 13 , wherein the second SMD further comprises a third and a fourth I/O pads disposed on one side of the first SMD, which are opposite to the first and the second I/O pads, the third I/O pad electrically connected to the first electrode through a seventh bonding wire and the fourth I/O pad electrically connected to the second electrode through an eighth bonding wire.

17. The semiconductor package according to claim 10 , further comprising:
a second substrate mounted on the second top surface of the second SMD; and
a first SMD element mounted on a third top surface of the second substrate departed from the second SMD.

18. The semiconductor package according to claim 17 , further comprising:
a second conductive layer formed of the third top surface; and
a ninth bonding wire electrically connecting the second conductive layer with the second top surface of the second SMD.

19. The semiconductor package according to claim 18 , further comprising a third SMD mounted on the third top surface and electrically connected to the first SMD.

20. The semiconductor package according to claim 17 , wherein a tenth bonding wire electrically connecting the first SMD with the first conductive layer.

Assignees

• Mediatek Inc

Inventors

• Chen Nan-Jang

Classifications

• H10W90/759

  between a chip and a laterally-adjacent discrete passive device · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title