Wafer scale packaging

Patent metadata

Field	Value
Publication number	US-9805966-B2
Application number	US-201414341314-A
Country	US
Kind code	B2
Filing date	Jul 25, 2014
Priority date	Jul 25, 2014
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

A method of wafer scale packaging acoustic resonator devices and an apparatus therefor. The method including providing a partially completed semiconductor substrate comprising a plurality of single crystal acoustic resonator devices, each having a first electrode member, a second electrode member, and an overlying passivation material. At least one of the devices to be configured with an external connection, a repassivation material overlying the passivation material, an under metal material overlying the repassivation material. Copper pillar interconnect structures are then configured overlying the electrode members, and solder bump structures are form overlying the copper pillar interconnect structures.

First claim

What is claimed is:

1. A wafer scale package apparatus, the apparatus comprising:
a partially completed semiconductor substrate, the semiconductor substrate comprising a plurality of single crystal acoustic resonator devices, each of the devices having a first electrode member, a second electrode member, and an overlying passivation material;
for at least one of the devices to be configured with an external connection, a repassivation material overlying the passivation material, the repassivation material having a first region exposing the first electrode member and a second region exposing the second electrode member;
an under metal material overlying the repassivation material and covering the first region and the second region such that the first electrode member and the second electrode member are each in electrical and physical contact with the under metal material;
a copper pillar interconnect structure configured to fill the first region and the second region using a deposition process to form a first copper pillar structure overlying the first electrode member and a second copper pillar structure overlying the second electrode member; and
a first solder bump structure overlying the first copper pillar structure and a second solder bump structure overlying the second copper pillar structure for the single crystal acoustic resonator device to be configured with the external connection.

2. The apparatus of claim 1 wherein each of the devices comprises
a substrate member, a surface region, and a backside region,
an epitaxial material comprising a single crystal piezo material overlying the surface region to a desired thickness,
a trench region to form an exposed portion of the surface region through a pattern provided in the epitaxial material,
a topside landing pad metal within a vicinity of the trench region and overlying the exposed portion of the surface region, the first electrode member overlying a portion of the epitaxial material, and the second electrode member overlying the topside landing pad metal,
a backside trench region exposing a backside of the epitaxial material overlying the first electrode member, and exposing a backside of the landing pad metal and a backside resonator metal material overlying the backside of the epitaxial material to form a connection from the epitaxial material to the backside of the landing pad metal to couple to the second electrode member overlying the topside landing pad metal.

3. The apparatus of claim 1 wherein the repassivation material comprises a cyclotene material having a thickness ranging from 1 um to 25 um.

4. The apparatus of claim 1 wherein the under metal material comprising a titanium containing and copper containing material.

5. The apparatus of claim 1 wherein the under metal material comprises a titanium containing and copper containing material;
wherein the under metal material has a thickness ranging from 0.1 um to 10 um.

6. The apparatus of claim 1 wherein the partially completed semiconductor substrate is configured to provide one single crystal acoustic resonator device on a first single chip from the plurality of single crystal acoustic resonator devices or is configured to provide either 2, 3, 5, 7, or 9 single crystal resonator devices provided on a second single chip;
wherein each of the solder bumps is configured on an outer peripheral region of the single chip.

7. The apparatus of claim 1 wherein the under metal material comprises a sputtering-deposited under metal material.

8. The apparatus of claim 1 wherein the copper pillar and solder material deposition process comprises a plating process.

9. The apparatus of claim 1 wherein each of the first solder bump structure and the second solder bump structure has a height of 20 um to 100 um and a width of 25 um to 150 um at a widest region.

10. The apparatus of claim 1 wherein the partially completed semiconductor substrate is configured to singulate each chip device using a saw and a break process.

11. The apparatus of claim 1 further comprising a flexible tape member.

12. The apparatus of claim 1 further comprising
a mounting substrate member; and
a molding material overlying each of the devices.

13. The apparatus of claim 1 further comprising
a mounting substrate member; and
a molding material overlying each of the devices;
wherein the partially completed semiconductor substrate is configured to the mounting substrate and encapsulated in the molding material.

14. A method of wafer scale packaging a grouping of single crystal acoustic resonator devices, the method comprising:
providing a partially completed semiconductor substrate, the semiconductor substrate comprising N number of single crystal acoustic resonator devices, each of the N devices having a first electrode member and a second electrode member, and an overlying passivation material, the N devices being numbered R 1 , R 2 , . . . R N−1 , and R N ;
for at least each of devices R 1 and R N , forming a repassivation material overlying the passivation material, the repassivation material having a first region exposing the first electrode member and a second region exposing the second electrode member;
forming an under metal material overlying the repassivation material and covering the first region and the second region such that the first electrode member and the second electrode member are each in electrical and physical contact with the under metal material;
forming a thickness of resist material overlying the under metal material to cause a substantially planarized surface region;
patterning the substantially planarized surface region of the thickness of resist material to expose a first region corresponding to the first electrode member and a second region corresponding to the second electrode member;
filling the first region and the second region using a deposition process to form a first copper pillar structure overlying the first electrode member and a second copper pillar structure overlying the second electrode member;
forming a solder material overlying the first copper pillar structure and the second copper pillar structure;
processing the thickness of resist material to substantially remove the thickness of resist material and expose the under metal material;
removing any exposed portions of the under metal material;
subjecting the solder material on the first copper pillar structure and the second copper pillar structure to cause formation of a first solder bump structure overlying the first copper pillar structure and a second solder bump structure overlying the second copper pillar structure for at least each of R 1 and R N .

15. The method of claim 14 wherein the repassivation material comprises a cyclotene material having a thickness ranging from 1 um to 25 um; wherein the under metal material comprising a titanium containing and copper containing material; wherein the under metal material has a thickness ranging from 0.1 um to 10 um.

16. The method of claim 14 wherein the resist material comprises AZ nLOF 2035 and is formed to the thickness ranging from 3 um to 6 um.

17. The method of claim 14 wherein the under metal material deposition process comprises a sputtering process;
wherein the copper pillar and solder material deposition process comprises a plating process; and
wherein each of the first solder bump structures and the second solder bump structures has a height of 20 um to 100 um and a width of 25 um to 150 um at a widest region.

18. The method of claim 14 further comprising subjecting the semico

Assignees

• Akoustis Inc

Inventors

• Shealy Jeffrey B

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W10/01

  Manufacture or treatment · CPC title

• H10W10/00 Primary

  Isolation regions in semiconductor bodies between components of integrated devices · CPC title

• H03H9/0523

  for flip-chip mounting · CPC title

• H03H2003/023

  the resonators or networks being of the membrane type · CPC title