High κ gate stack on III-V compound semiconductors

Patent metadata

Field	Value
Publication number	US-9805949-B2
Application number	US-201213607741-A
Country	US
Kind code	B2
Filing date	Sep 9, 2012
Priority date	Jan 6, 2006
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

A method of forming a high k gate stack on a surface of a III-V compound semiconductor, such GaAs, is provided. The method includes subjecting a III-V compound semiconductor material to a precleaning process which removes native oxides from a surface of the III-V compound semiconductor material; forming a semiconductor, e.g., amorphous Si, layer in-situ on the cleaned surface of the III-V compound semiconductor material; and forming a dielectric material having a dielectric constant that is greater than silicon dioxide on the semiconducting layer. In some embodiments, the semiconducting layer is partially or completely converted into a layer including at least a surface layer that is comprised of AO x N y prior to forming the dielectric material. In accordance with the present invention, A is a semiconducting material, preferably Si, x is 0 to 1, y is 0 to 1 and x and y are both not zero.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a III-V compound semiconductor material having a topmost surface that is essentially free of native oxides;
a material stack located on said III-V compound semiconductor material; and
a source/drain diffusion region located adjacent a pair of opposing sides of, and spaced apart from, said material stack, wherein each source/drain diffusion region has a topmost surface that is located above said topmost surface of said III-V compound semiconductor material and a bottommost surface that contacts a portion of said III-V compound semiconductor material that is located beneath said topmost surface of III-V compound semiconductor material, wherein said material stack comprises:
a base semiconductor layer comprising a first semiconductor material located directly on said topmost surface of said III-V compound semiconductor material, wherein the first semiconductor material includes at least one of Ge alloys, SiGe, SiC and SiGeC;
a layer of AO x N y located on an upper portion of said base semiconductor layer, wherein A is said first semiconductor material, x is from 0 to 1, y is from 0 to 1, with the proviso that when x is 0, y is not 0 or when y is 0, x is not 0, and wherein an interface is present between said topmost surface of said III-V compound semiconductor material and a bottommost surface of said base semiconductor layer that has an interface state density of about 10 12 cm −2 eV −1 or less, and
a dielectric material located directly on said layer of AO x N y , said dielectric material having a dielectric constant that is greater than silicon dioxide and comprising a metal oxide or a mixed metal oxide.

2. The semiconductor structure of claim 1 , wherein said base semiconductor layer is amorphous.

3. The semiconductor structure of claim 1 , wherein said dielectric material is a Hf-based dielectric.

4. The semiconductor structure of claim 3 , wherein said dielectric material is a single layer that is in directed contact with said layer of AO x N y .

5. The semiconductor structure of claim 1 , further comprising an electrode or electrode stack on said dielectric material.

6. The semiconductor structure of claim 1 , wherein said dielectric material is a component of at least one field effect transistor.

Assignees

• Fompeyrine Jean
• Kiewra Edward W
• Koester Steven J
• Sadana Devendra K
• Webb David J
• Globalfoundries Inc

Inventors

• Fompeyrine Jean
• Kiewra Edward W
• Koester Steven J
• Sadana Devendra K
• Webb David J

Classifications

• H10P14/69392

  the material containing hafnium, e.g. HfO2 · CPC title

• H10P14/6334

  using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329) · CPC title

• H10P14/693

  the material containing hafnium, e.g. HfSiOx or HfSiON · CPC title

• H10P14/412

  Deposition of metallic or metal-silicide materials · CPC title

• H10D64/01332 Primary

  Making the insulator · CPC title