Memory cell with retention using resistive memory

Patent metadata

Field	Value
Publication number	US-9805790-B2
Application number	US-201315025229-A
Country	US
Kind code	B2
Filing date	Dec 5, 2013
Priority date	Dec 5, 2013
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

Described is an apparatus including memory cell with retention using resistive memory. The apparatus comprises: memory element including a first inverting device cross-coupled to a second inverting device; a restore circuit having at least one resistive memory element, the restore circuit coupled to an output of the first inverting device; a third inverting device coupled to the output of the first inverting device; a fourth inverting device coupled to an output of the third inverting device; and a save circuit having at least one resistive memory element, the save circuit coupled to an output of the third inverting device.

First claim

We claim:

1. An apparatus comprising:
a memory element including a first inverting device cross-coupled to a second inverting device;
a restore circuit having at least one resistive memory element and at least two input signals to enable the restore circuit, the restore circuit coupled to an output of the first inverting device;
a third inverting device coupled to the output of the first inverting device;
a fourth inverting device coupled to an output of the third inverting device; and
a save circuit having at least one resistive memory element and at least two input signals to enable the save circuit, the save circuit coupled to an output of the third inverting device.

2. The apparatus of claim 1 , wherein the first inverting device is controllable by a clock signal.

3. The apparatus of claim 2 further comprises a transmission gate coupled to the memory element, the transmission gate controllable by the clock signal such that when the transmission gate is turned on, the first inverting device is in tri-state.

4. The apparatus of claim 1 , wherein the save circuit comprises:
a first logic unit coupled to the output of the first inverting device, the first logic unit to also receive a signal; and
a second logic unit coupled to the output of the fourth inverting device, the second logic unit to also receive the signal.

5. The apparatus of claim 4 , wherein the first and second logic units are NAND gates.

6. The apparatus of claim 4 , wherein the save circuit further comprises:
a first p-type device coupled in series to a first n-type device;
a second p-type device coupled in series to a second n-type device; and
a first resistive element coupled to the first and second p-type devices and to the first and second n-type devices, wherein the first and second p-type devices and the first and second n-type devices are controllable by outputs of the first and second logic units.

7. The apparatus of claim 6 , wherein the first resistive element is a Magnetic Tunnel Junction (MTJ) device including:
a free magnetic layer coupled to the first p-type device and the first n-type device; and
a fixed magnetic layer coupled to the second p-type device and the second n-type device.

8. The apparatus of claim 4 , wherein the save circuit further comprises:
a third p-type device coupled in series to a third n-type device;
a fourth p-type device coupled in series to a fourth n-type device; and
a second resistive element coupled to the third and fourth p-type devices and to the third and fourth n-type devices, wherein the third and fourth p-type devices and the third and fourth n-type devices are controllable by outputs of the first and second logic units.

9. The apparatus of claim 8 , wherein the second resistive element is a Magnetic Tunnel Junction (MTJ) device including:
a free magnetic layer coupled to the third p-type device and the third n-type device; and
a fixed magnetic layer coupled to the fourth p-type device and the fourth n-type device.

10. The apparatus of claim 1 , wherein the restore circuit comprises:
a first p-type device coupled to a power supply node;
a first resistive element coupled to the first p-type device; and
a second p-type device coupled to the first resistive element and the output of the first inverting device.

11. The apparatus of claim 10 , wherein the first resistive element is a Magnetic Tunnel Junction (MTJ) device including:
a free magnetic layer coupled to the first p-type device; and
a fixed magnetic layer coupled to the second p-type device.

12. The apparatus of claim 10 , wherein the restore circuit comprises:
a first n-type device coupled to a ground node;
a second resistive element coupled to the first n-type device; and
a second n-type device coupled to the second resistive element and the output of the first inverting device, the second n-type device further coupled to the second p-type device.

13. The apparatus of claim 10 , wherein the second resistive element is a Magnetic Tunnel Junction (MTJ) device including:
a free magnetic layer coupled to the first n-type device; and
a fixed magnetic layer coupled to the second n-type device.

14. The apparatus of claim 1 , wherein the at least one resistive memory element of the restore circuit and the save circuit is at least one of:
magnetic tunnel junction (MTJ) device;
conductive bridge RAM (CBRAM), or
bi-stable organic memories.

15. The apparatus of claim 1 further comprises:
another restore circuit having at least one resistive memory element, the other restore circuit coupled to an output of the second inverting device.

16. The apparatus of claim 1 further comprises:
another save circuit having at least one resistive memory element, the save circuit coupled to the outputs of the third and fourth inverting devices.

17. The apparatus of claim 1 , wherein the memory element is part of one of:
a flip-flop;
a latch; or
a static random memory.

18. A system comprising:
a memory unit;
a processor, coupled to the memory unit, the processor including an apparatus according to any one of apparatus claims 1 to 17 ; and
a wireless interface for allowing the processor to communicate with another device.

19. The system of claim 18 further comprises a display unit.

20. The system of claim 19 , wherein the display unit is a touch screen.

Assignees

• Intel Corp

Inventors

• August Nathaniel J
• Jain Pulkit
• Rusu Stefan
• Hamzaoglu Fatih
• Venkatesan Rangharajan
• Khellah Muhammad
• Augustine Charles
• Tokunaga Carlos
• Tschanz James W
• Wang Yih

Classifications

• G11C11/1693

  Timing circuits or methods · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11C11/1659

  Cell access · CPC title

• G11C14/009

  and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material · CPC title