Semiconductor memory device, a memory module including the same, and a memory system including the same

Patent metadata

Field	Value
Publication number	US-9805774-B2
Application number	US-201715426603-A
Country	US
Kind code	B2
Filing date	Feb 7, 2017
Priority date	May 29, 2014
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

A semiconductor memory device includes a ZQ calibration unit configured to generate a pull-up VOH code according to a first target VOH proportional to a power supply voltage and an output driver configured to generate a data signal having a VOH proportional to the power supply voltage based on the pull-up VOH code, wherein VOH means “output high level voltage.”

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a pull-up VOH control block configured to generate a first target VOH, the voltage level of the first target VOH being proportional to a power supply voltage (VDDQ);
a ZQ calibration unit, during a ZQ calibration operation, configured to generate a pull-up VOH code in accordance with the first target VOH; and
an output driver configured to generate a data signal having a first VOH level based on the pull-up VOH code, the first VOH level being an output high level voltage proportional to the power supply voltage,
wherein the first target VOH has a voltage level of VDDQ/2.5 or VDDQ/3.

2. The semiconductor memory device of claim 1 , wherein the ZQ calibration unit includes a first calibration unit configured to generate the pull-up VOH code, which determines a current generated by a pull-up driver of the output driver, based on the first target VOH.

3. The semiconductor memory device of claim 2 , wherein the ZQ calibration unit further includes a second calibration unit configured to generate a pull-down VOH code, which determines a resistance of a pull-down driver of the output driver, based on a second target VOH.

4. The semiconductor memory device of claim 2 , wherein the first calibration unit comprises:
a first comparator configured to output a first comparison result by comparing the first target VOH with a voltage at a first node;
a first code generator configured to generate the pull-up VOH code based on the first comparison result;
a replica pull-up driver configured to generate a first current at the first node based on the pull-up VOH code; and
a replica on-die termination (ODT) resistor configured to determine the voltage at the first node according to the first current.

5. The semiconductor memory device of claim 4 , wherein the resistance of the replica ODT resistor is set to have a substantially same resistance with an ODT resistor of a memory controller communicating with the semiconductor memory device.

6. The semiconductor memory device of claim 5 , wherein if a resistance of the replica ODT resistor is one of 80Ω, 120Ω, and 240Ω, the first target VOH is set to have voltage level of VDDQ/3, and if a resistance of the replica ODT resistor is one of 34Ω, 40Ω, 60Ω, 80Ω, 120Ω, and 240Ω, the first target VOH is set to have voltage level of VDDQ/2.5 or VDDQ/3.

7. The semiconductor memory device of claim 1 , wherein the pull-up VOH control block includes a first voltage divider configured to generate VDDQ/3 and a second voltage divider configured to generate VDDQ/2.5, and a selection circuit configured to select one of VDDQ/3 and VDDQ/2.5 as the first target VOH according to an MRS signal.

8. The semiconductor memory device of claim 1 , wherein the first target VOH is set during mode register set (MRS) programming.

9. The semiconductor memory device of claim 1 , wherein the power supply voltage (VDDQ) is a data output power supply voltage.

10. The semiconductor memory device of claim 1 , wherein the output driver is a low voltage swing terminated logic (LVSTL) output driver.

11. A memory system, comprising:
a memory controller including an on-die termination (ODT) resistor for receiving a data signal; and
a semiconductor memory device configured to send the data signal to the memory controller through a data bus, the semiconductor memory device comprising:
a pull-up VOH control block configured to generate a first target VOH proportional to a power supply voltage (VDDQ), the first target VOH being one of VDDQ/2.5 and VDDQ/3;
a ZQ calibration unit, upon receiving the first target VOH, configured to generate a pull-up VOH code according to the first target VOH; and
an output driver configured to generate a data signal having a first VOH level based on the pull-up VOH code, the first VOH level being an output high level voltage proportional to the power supply voltage.

12. The memory system of claim 11 , wherein the ZQ calibration unit includes a first calibration unit configured to generate the pull-up VOH code, which determines a current generated by a pull-up driver of the output driver, based on the first target VOH.

13. The memory system of claim 12 , wherein the ZQ calibration unit further includes a second calibration unit configured to generate a pull-down VOH code, which determines a resistance of a pull-down driver of the output driver, based on a second target VOH.

14. The memory system of claim 12 , wherein the first calibration unit comprises:
a first comparator configured to output a first comparison result by comparing the first target VOH with a voltage at a first node;
a first code generator configured to generate the pull-up VOH code based on the first comparison result;
a replica pull-up driver configured to generate a first current at the first node based on the pull-up VOH code; and
a replica on-die termination (ODT) resistor configured to determine the voltage at the first node according to the first current.

15. The memory system of claim 14 , wherein the resistance of the replica ODT resistor is set to have a substantially same resistance with the ODT resistor of the memory controller.

16. The memory system of claim 15 , wherein if a resistance of the ODT resistor is one of 80Ω, 120Ω, and 240Ω, the first target VOH is set to have voltage level of VDDQ/3, and if a resistance of the ODT resistor is one of 34Ω, 40Ω, 60Ω, 80Ω, 120Ω, and 240Ω, the first target VOH is set to have voltage level of VDDQ/2.5 or VDDQ/3.

17. The memory system of claim 11 , wherein the pull-up VOH control block includes a first voltage divider configured to generate VDDQ/3 and a second voltage divider configured to generate VDDQ/2.5, and a selection circuit configured to select one of VDDQ/3 and VDDQ/2.5 as the first target VOH according to an MRS signal.

18. The memory system of claim 11 , wherein the first target VOH is set during mode register set (MRS) programming.

19. The memory system of claim 11 , wherein the power supply voltage (VDDQ) is a data output power supply voltage.

20. The memory system of claim 11 , wherein the output driver is a low voltage swing terminated logic (LVSTL) output driver.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Ki Won
• Bae Seung Jun
• Park Joon Young
• Bae Yong Cheol

Classifications

• G11C7/12 Primary

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• H03K19/0005

  Modifications of input or output impedance · CPC title

• G11C2207/2254

  Calibration · CPC title

• G11C7/1057

  Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C5/147

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title