Display controller, video signal transmitting method and system thereof for transmitting video signals with multiple data rate and reduced numbers of signals line

Patent metadata

Field	Value
Publication number	US-9805685-B2
Application number	US-82291410-A
Country	US
Kind code	B2
Filing date	Jun 24, 2010
Priority date	Jul 1, 2009
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

A display controller, video signal transmitting method and system thereof are provided. The display controller includes a processing circuit; a transmitting channel, coupled to the processing circuit; a receiving channel, coupled to the processing circuit; and a clock generator, that generates an internal clock signal and an external clock signal. Upon receiving a video signal, the processing circuit processes a first partial pixel data of the video signal to output a first display control signal. The transmitting channel converts a second partial pixel data of the video signal to a partial video signal having a multiple data rate according to the internal clock signal to be outputted.

First claim

What is claimed is:

1. A method implemented in a first display controller, the method comprising:
receiving, by a processing circuit of the first display controller, a video signal;
converting, by the processing circuit, a first partial pixel data of the video signal to output a first display control signal, the first display control signal including data displayed in a first portion of a frame;
generating, by a clock generator of an interface circuit of the first display controller, an external clock signal; and
processing, by the interface circuit, a second partial pixel data of the video signal to output a partial video signal to a second display controller, the partial video signal being outputted together with the external clock signal, the partial video signal including data displayed in a second portion of the frame, the first and the second portions being different portions of the frame,
wherein the partial video signal comprises a data enable (DE) signal, a horizontal synchronization signal, a vertical synchronization signal, a red data, a blue data and a green data, and
wherein the partial video signal is transmitted with a multiple data rate per clock cycle of the external clock signal such that a number of signal lines needed by the partial video signal is reduced.

2. The method as claimed in claim 1 , further comprising:
receiving the partial video signal and the external clock signal by the second display controller;
retrieving the second partial pixel data from the partial video signal according to the external clock signal by the second display controller; and
converting the second partial pixel data to a second display control signal and outputting the second display control signal by second display controller.

3. The method as claimed in claim 2 , further comprising:
displaying the frame according to the first display control signal and the second display control signal by a liquid crystal display (LCD) panel.

4. The method as claimed in claim 1 , further comprising:
applying a clock signal from a plurality of clock signals in sequence as the external clock signal to output a test data signal by the first display controller;
recording a plurality of operative clock signals from the plurality of clock signals according to a sampling result by sampling the test data signal by the second display controller; and
selecting one operative clock signal from the plurality of operative clock signals as the external clock signal.

5. An apparatus, comprising:
a first display controller that receives a video signal and converts a first partial pixel data of the video signal to a first display control signal that includes data displayed in a first portion of a frame, and converts a second partial pixel data of the video signal to a partial video signal according to an internal clock signal, the partial video signal being outputted together with an external clock signal generated by a clock generator of the first display controller; and
a second display controller that receives the partial video signal and the external clock signal, converts the partial video signal to the second partial pixel data, and converts the second partial pixel data to a second display control signal that includes data displayed in a second portion of the frame, the first and the second portions being different portions of the frame,
wherein the first display control signal and the second display control signal are used to control an LCD panel to display the frame,
wherein the partial video signal comprises a data enable (DE) signal, a horizontal synchronization signal, a vertical synchronization signal, a red data, a blue data and a green data, and
wherein the partial video signal is transmitted with a multiple data rate per clock cycle of the external clock signal such that a number of signal lines needed by the partial video signal is reduced.

6. The apparatus as claimed in claim 5 , wherein the partial video signal is transmitted with a multiple data rate with reference with the external clock signal.

7. The apparatus as claimed in claim 5 , wherein the first display controller comprises a TX channel that converts the second partial pixel data to the partial video signal, and outputs the partial video signal.

8. The apparatus as claimed in claim 7 , wherein the TX channel comprises:
a TX buffer that temporarily stores the second partial pixel data; and
a TX data packaging unit that converts the second pixel data outputted by the TX buffer to the partial video signal with a multiple data rate.

9. The apparatus as claimed in claim 8 , wherein the TX data packaging unit comprises a data packaging circuit that packages two bit lines for the second partial pixel data to one bit line for the partial video signal.

10. An apparatus, comprising:
a display controller comprising:
a clock generator, for generating an external clock signal;
a processing circuit, for receiving a video signal, processing a first partial pixel data of the video signal to output a first display control signal, and outputting a second partial pixel data of the video signal; and
an interface circuit, for receiving the second partial pixel data from the processing circuit, and outputting a partial video signal together with the external clock signal according to the second partial pixel data to another display controller to output a second display control signal accordingly,

wherein the first display control signal comprises data displayed in a first portion of a frame and the second display control signal comprises data displayed in a second portion of the frame, and
wherein the interface circuit comprises a packing unit that packages the second partial pixel data into the partial video signal.

11. The apparatus as claimed in claim 10 , wherein the second partial pixel data is in 2 N signal lines and the partial video signal is in N signal lines.

12. The apparatus as claimed in claim 11 , wherein each signal line of the second partial pixel data is a single data rate signal and each signal line of the partial video signal is a double data rate signal.

13. The apparatus as claimed in claim 10 , wherein the packing unit packaging two bit lines of the second partial pixel data into one bit lines of the partial video signal.

14. The apparatus as claimed in claim 10 , wherein the clock generator generates an internal clock signal to the packing unit, and wherein the packing unit packages the second partial pixel data into the partial video signal according to the transitions of the internal clock signal.

Assignees

• Lin Chen-Nan
• Yeh Ming-Chieh
• Yeh Chun Wen
• Chen Chun-Chia
• Mstar Semiconductor Inc

Inventors

• Lin Chen-Nan
• Yeh Ming-Chieh
• Yeh Chun Wen
• Chen Chun-Chia

Classifications

• G09G2310/027

  Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters · CPC title

• G09G3/3685 Primary

  Details of drivers for data electrodes · CPC title

• G09G2310/0221

  with use of split matrices (G09G3/3644 and G09G3/3666 take precedence) · CPC title

• G09G2352/00

  Parallel handling of streams of display data · CPC title