Instruction-set support for invocation of VMM-configured services without VMM intervention

Patent metadata

Field	Value
Publication number	US-9804871-B2
Application number	US-201313843337-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Oct 28, 2011
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

A processing core comprising instruction execution logic circuitry and register space. The register space to be loaded from a VMCS, commensurate with a VM entry, with information indicating whether a service provided by the processing core on behalf of the VMM is enabled. The instruction execution logic to, in response to guest software invoking an instruction: refer to the register space to confirm that the service has been enabled, and, refer to second register space or memory space to fetch input parameters for said service written by said guest software.

First claim

What is claimed is:

1. A method performed by a processor comprising:
writing, into a virtual machine control structure (VMCS), an indication that an instruction is enabled for a virtual machine of the processor, and a plurality of services the processor is to perform without exiting the virtual machine;
loading, upon entry into the virtual machine, the indication from the VMCS into register space of the processor;
receiving a request from the virtual machine, to perform the instruction;
decoding the instruction into a decoded instruction with a decode unit of the processor; and
executing the decoded instruction with an execution unit of the processor to:
check if the instruction, requested for execution by the virtual machine of the processor, is enabled for the virtual machine by reading the register space,
check if a service requested by the virtual machine of the processor is one of the plurality of services the processor is to perform without exiting the virtual machine by reading the register space, wherein the plurality of services comprises at least one non-interrupt service the processor is to perform without exiting the virtual machine, and
perform the service without exiting the virtual machine if the instruction is enabled for the virtual machine and the service is one of the plurality of services.

2. The method of claim 1 , wherein the register space of the processor comprises a private control register space of the processor.

3. The method of claim 1 , wherein the check of the service comprises the virtual machine loading a value that identifies the service requested into a register of the processor.

4. The method of claim 3 , wherein the check of the service further comprises comparing configuration information for the plurality of services the processor is to perform without exiting the virtual machine for the virtual machine in the register space of the processor with the value.

5. The method of claim 1 , wherein the check of the service comprises the virtual machine loading a value that identifies the service requested into a memory of the processor.

6. The method of claim 5 , wherein the check of the service further comprises comparing configuration information for the plurality of services the processor is to perform without exiting the virtual machine for the virtual machine in the register space of the processor with the value.

7. The method of claim 1 , wherein the plurality of services comprises a plurality of non-interrupt services the processor is to perform without exiting the virtual machine.

8. A processor comprising:
a decode unit to decode an instruction into a decoded instruction in response to receiving a request from a virtual machine to perform the instruction; and
an execution unit to execute the decoded instruction to:
check if the instruction, requested for execution by the virtual machine of the processor, is enabled for the virtual machine by reading a register space of the processor,
check if a service requested by the virtual machine of the processor is one of a plurality of services the processor is to perform without exiting the virtual machine by reading the register space, wherein the plurality of services comprises at least one non-interrupt service the processor is to perform without exiting the virtual machine, and
perform the service without exiting the virtual machine if the instruction is enabled for the virtual machine and the service is one of the plurality of services, wherein a virtual machine control structure (VMCS) is to store an indication that the instruction is enabled for the virtual machine of the processor, and the plurality of services the processor is to perform without exiting the virtual machine, and the indication is loaded into the register space of the processor from the VMCS upon entry into the virtual machine.

9. The processor of claim 8 , wherein the register space of the processor comprises a private control register space of the processor.

10. The processor of claim 8 , wherein the check of the service comprises the virtual machine to load a value that identifies the service requested into a register of the processor.

11. The processor of claim 10 , wherein the check of the service further comprises a comparison of configuration information for the plurality of services the processor is to perform without exiting the virtual machine for the virtual machine in the register space of the processor with the value.

12. The processor of claim 8 , wherein the check of the service comprises the virtual machine to load a value that identifies the service requested into a memory of the processor.

13. The processor of claim 12 , wherein the check of the service further comprises a comparison of configuration information for the plurality of services the processor is to perform without exiting the virtual machine for the virtual machine in the register space of the processor with the value.

14. The processor of claim 8 , wherein the plurality of services comprises a plurality of non-interrupt services the processor is to perform without exiting the virtual machine.

15. A non-transitory machine readable medium containing stored program code that when processed by a machine causes a method to be performed, said method comprising:
writing, into a virtual machine control structure (VMCS), an indication that an instruction is enabled for a virtual machine of the processor, and a plurality of services the processor is to perform without exiting the virtual machine;
loading, upon entry into the virtual machine, the indication from the VMCS into register space of the processor;
receiving a request from the virtual machine, to perform the instruction;
decoding the instruction into a decoded instruction with a decode unit of the processor; and
executing the decoded instruction with an execution unit of the processor to:
check if the instruction, requested for execution by the virtual machine of the processor, is enabled for the virtual machine by reading the register space,
check if a service requested by the virtual machine of the processor is one of the plurality of services the processor is to perform without exiting the virtual machine by reading the register space, wherein the plurality of services comprises at least one non-interrupt service the processor is to perform without exiting the virtual machine, and
perform the service without exiting the virtual machine if the instruction is enabled for the virtual machine and the service is one of the plurality of services.

16. The non-transitory machine readable medium of claim 15 , wherein the register space of the processor comprises a private control register space of the processor.

17. The non-transitory machine readable medium of claim 15 , wherein the check of the service comprises the virtual machine loading a value that identifies the service requested into a register of the processor.

18. The non-transitory machine readable medium of claim 17 , wherein the check of the service further comprises comparing configuration information for the plurality of services the processor is to perform without exiting the virtual machine for the virtual machine in the register space of the processor with the value.

19. The non-transitory machine readable medium of claim 15 , wherein the check of the service comprises the virtual machine loading a value that identifies the service requested into a memory of the processor.

20. The non-transitory machine readable medium of claim 19 , wherein the check of

Assignees

• Intel Corp

Inventors

• Neiger Gilbert
• Huntley Barry E
• Sahita Ravi L
• Shanbhogue Vedvyas
• Brandt Jason W

Classifications

• G06F9/455

  Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines · CPC title

• G06F9/4555 Primary

  Para-virtualisation, i.e. guest operating system has to be modified · CPC title

• G06F9/45533

  Hypervisors; Virtual machine monitors · CPC title

• G06F9/45545 Primary

  Guest-host, i.e. hypervisor is an application program itself, e.g. VirtualBox · CPC title