Instruction and logic to provide stride-based vector load-op functionality with mask duplication

Patent metadata

Field	Value
Publication number	US-9804844-B2
Application number	US-201113977728-A
Country	US
Kind code	B2
Filing date	Sep 26, 2011
Priority date	Sep 26, 2011
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

Instructions and logic provide vector load-op and/or store-op with stride functionality. Some embodiments, responsive to an instruction specifying: a set of loads, a second operation, destination register, operand register, memory address, and stride length; execution units read values in a mask register, wherein fields in the mask register correspond to stride-length multiples from the memory address to data elements in memory. A first mask value indicates the element has not been loaded from memory and a second value indicates that the element does not need to be, or has already been loaded. For each having the first value, the data element is loaded from memory into the corresponding destination register location, and the corresponding value in the mask register is changed to the second value. Then the second operation is performed using corresponding data in the destination and operand registers to generate results. The instruction may be restarted after faults.

First claim

What is claimed is:

1. A processor comprising:
a first register to have a first plurality of data fields, wherein each of the first plurality of data fields in the first register is to correspond to a multiple of a stride length from a beginning address for a corresponding data element to be in a memory, wherein for each of the first plurality of data fields, a first value is to indicate the corresponding data element has not yet been loaded from the memory and a second value is to indicate that the corresponding data element does not need to be loaded, or has already been loaded from the memory;
a decode stage to decode a first instruction that is to specify the first register, a set of load operations corresponding to one or more of the first plurality of data fields, and a second single-instruction-multiple-data (SIMD) operation; and
one or more execution units, responsive to the decoded first instruction, to:
duplicate the first plurality of data fields of the first register;
read values of each of the first plurality of data fields of the first register;
for each data field of the first plurality of data fields that is to have the first value, obtain the corresponding data element from the memory and store the corresponding data element into a second register, the second register to have a second plurality of data fields, a portion of which to store the obtained data elements, and change the value of the data field of the first register from the first value to the second value; and
perform the second SIMD operation using data elements that are to be received from the portion of the second plurality of data fields to generate corresponding result data elements.

2. The processor of claim 1 , wherein the first value is one.

3. The processor of claim 1 , wherein the second value is zero.

4. The processor of claim 1 , wherein said one or more execution units, responsive to the decoded first instruction, are to use the duplicate of the first plurality of data fields of the first register when the second SIMD operation is performed.

5. The processor of claim 4 , wherein said one or more execution units, responsive to the decoded first instruction, are to duplicate each of the first plurality of data fields that is to have the first value in the first register when the value of that data field in the first register is changed from the first value to the second value.

6. The processor of claim 1 , wherein said one or more execution units are to use the duplicated first plurality of data fields to perform the second SIMD operation, either upon a fault or after each data field of the first plurality of data fields in the first register has the second value.

7. The processor of claim 1 , wherein the second SIMD operation is unary.

8. The processor of claim 1 , wherein the second SIMD operation is binary.

9. The processor of claim 1 , wherein the data elements to be stored into the second register are to be 32-bit data elements.

10. The processor of claim 1 , wherein the data elements to be stored into the second register are to be 64-bit data elements.

11. The processor of claim 1 , wherein the second register is a 512-bit vector register.

12. A non-transitory machine-readable medium to record functional descriptive material including a first executable instruction, which if executed by a machine, is to cause the machine to:
duplicate a first plurality of data fields that are to be in a first register;
read a value of each data field of the first plurality of data fields in the first register, wherein each of the first plurality of data fields is to correspond to a multiple of a stride length from a beginning address for a corresponding data element to be in a memory, and wherein for each data field of the first plurality of data fields, a first value is to indicate that the corresponding data element has not been loaded from the memory and a second value is to indicate that the corresponding data element does not need to be loaded, or has already been loaded from the memory;
for each data field of the first plurality of data fields that is to have the first value, retrieve the corresponding data element from the memory and store the corresponding data element into a second register, the second register to have a second plurality of data fields, a portion of which to store the retrieved data elements, and change the value of the data field in the first register from the first value to the second value; and then perform a second single-instruction-multiple-data (SIMD) operation using the retrieved data elements of said portion of the second plurality of data fields to generate corresponding result data elements.

13. The non-transitory machine-readable medium of claim 12 , wherein the first executable instruction, if executed by the machine, is to cause the machine to:
use the duplicate of the first plurality of data fields when the second SIMD operation is performed.

14. The non-transitory machine-readable medium of claim 12 , wherein the first executable instruction, if executed by the machine, is to cause the machine to:
duplicate each of the first plurality of data fields that is to have the first value in the first register when the value of that data field in the first register is changed from the first value to the second value.

15. The non-transitory machine-readable medium of claim 12 , wherein the first executable instruction, if executed by the machine, is to cause the machine to:
use the duplicated first plurality of data fields to perform the second SIMD operation, either upon a fault or after each data field of the first plurality of data fields in the first register has the second value.

16. The non-transitory machine-readable medium of claim 12 , wherein the second SIMD operation is unary.

17. The non-transitory machine-readable medium of claim 12 , wherein the second SIMD operation is binary.

18. The non-transitory machine-readable medium of claim 12 , wherein the data elements to be stored into the second register are to be 32-bit data elements.

19. The non-transitory machine-readable medium of claim 12 , wherein the data elements to be stored into the second register are to be 64-bit data elements.

20. The non-transitory machine-readable medium of claim 12 , wherein the second register is a 512-bit vector register.

21. A processor comprising:
a decode stage to decode a first single-instruction-multiple-data (SIMD) instruction that is to specify: a set of load operations and a second SIMD operation, a destination register, an operand register, a memory address, and a stride length; and
one or more execution units, responsive to the decoded first SIMD instruction, to:
duplicate a first plurality of data fields of a mask register;
read values of each data field of the first plurality of data fields of the mask register, wherein each of the first plurality of data fields is to correspond to a multiple of the stride length from the memory address for a corresponding data element to be in a memory, and wherein for each data field of the first plurality of data fields, a first value is to indicate the corresponding data element has not been loaded from the memory and a second value is to indicate that the corresponding data element does not need to be loaded, or has already been loaded from the memory;
for each data field of the first plurality of data fields that is to have the first value, load the corresponding data element from the memory into a corresponding data field in the d

Assignees

• Ould-Ahmed-Vall Elmoustapha
• Doshi Kshitij A
• Sair Suleyman
• Yount Charles R
• Intel Corp

Inventors

• Ould-Ahmed-Vall Elmoustapha
• Doshi Kshitij A
• Sair Suleyman
• Yount Charles R

Classifications

• G06F9/30101

  Special purpose registers · CPC title

• G06F9/30185

  according to one or more bits in the instruction, e.g. prefix, sub-opcode · CPC title

• G06F9/30043 Primary

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/3455

  using stride · CPC title

• G06F9/383

  Operand prefetching (cache prefetching G06F12/0862) · CPC title